Hsic Interface - u-blox LARA-R203 System Integration Manual

2.6.3 HSIC interface

2.6.3.1 Guidelines for HSIC circuit design
The HSIC interface is not supported by the "02" and "62" product versions except for diagnostic purposes.
LARA-R2 series modules include a USB High-Speed Inter-Chip compliant interface with a maximum 480 Mb/s data
rate according to the High-Speed Inter-Chip USB Electrical Specification Version 1.0 [10] and USB Specification
Revision 2.0 [9]. The module itself acts as a device and can be connected to any compatible host.
The HSIC interface consists of a bi-directional DDR data line (HSIC_DATA) for transmitting and receiving data
synchronously with the bi-directional strobe line (HSIC_STRB), intended to be directly connected to the Data and
Strobe pins of the compatible USB High-Speed Inter-Chip host mounted on the same PCB of the LARA-R2 series
module, without using connectors / cables, as described in Figure 61.
The modules include also the HOST_SELECT pin to select the module / host application processor configuration:
the pin is available to select, enable, connect, disconnect and subsequently re-connect the HSIC interface.
USB HSIC
HOST PROCESSOR
DATA
STROBE
GND
Figure 61: HSIC interface application circuit
Further guidelines for HSIC interface circuit design will be described in detail in a successive release of the
System Integration Manual.
ESD sensitivity rating of HSIC interface pins is 1 kV (HBM as per JESD22-A114). Higher protection level could
be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g.
EPCOS CA05P4S14THSG varistor array) close to accessible points
If the HSIC interface pins are not used, they can be left unconnected on the application board, but it is
recommended to provide accessible test points directly connected to the HSIC_DATA and HSIC_STRB pins.
UBX-16010573 - R12
LARA-R2 series
HSIC_DATA
99
HSIC_STRB
100
GND
LARA-R2 series - System Integration Manual
Design-in
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