Table of Contents
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Function
Pin Name
System
PWR_ON
RESET_N
HOST_SELECT 21
Antenna
ANT1
ANT2
ANT_DET
SIM
VSIM
SIM_IO
SIM_CLK
SIM_RST
UBX-16010573 - R12
Pin No
I/O
Description
15
I
Power-on input
18
I
External reset
input
I/O
Selection of
module / host
configuration
56
I/O
Primary antenna
62
I
Secondary antenna
59
I
Input for antenna
detection
41
O
SIM supply output
39
I/O
SIM data
38
O
SIM clock
40
O
SIM reset
LARA-R2 series - System Integration Manual
Remarks
Internal 10 k pull-up resistor to V_BCKP.
See section 1.6.1 for functional description.
See section 2.3.1 for external circuit design-in.
Internal 10 k pull-up resistor to V_BCKP.
Test-Point for diagnostic access is recommended.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Not supported by "02" and "62" product versions.
Pin available to select, enable, connect, disconnect and
subsequently re-connect the HSIC interface.
Test-Point for diagnostic access is recommended.
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
Main Tx / Rx antenna interface.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and compliance of
the device integrating the module with applicable required
certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
Rx only for Rx diversity.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and compliance of
the device integrating the module with applicable required
certification schemes.
See section 1.7 for description and requirements.
See section 2.4 for external circuit design-in.
ADC for antenna presence detection function.
See section 1.7.2 for functional description.
See section 2.4.2 for external circuit design-in.
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
System description
Page 13 of 157
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