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7.3 Schematics
Figure 7-7
and
Figure 7-8
contain the schematics for the ADS131B26Q1EVM-PDK.
J5
ADC2A_V7A
ADC2A_V1A
1
ADC2A_V6A
2
3
ADC2A_V5A
R1
4
ADC2A_V4A
10.5k
5
ADC2A_V3A
6
ADC2A_V2A
R11
10.5k
J1
1
ADC2A_V1A
R10
2
ADC2A_V0A
3.00k
3
ADC3A_VPA
4
ADC3A_VNA
5
ADC1A_CPA
6
ADC1A_CNA
AGND
ADC_AVDD
ADC2A_V2A
ADC2A_V7A
R33
R67
R62
10.5k
DNP
DNP
10.0k
0
V7A
R34
R68
10.5k
DNP
DNP
C26
10.0k
100nF
R38
3.00k
AGND
AGND
J3
ADC3B_VNB
ADC2B_V1B
1
ADC3B_VPB
2
ADC1B_CNB
R6
3
ADC1B_CPB
10.5k
4
ADC2B_V0B
5
ADC2B_V1B
6
R17
10.5k
J4
1
ADC2B_V2B
2
ADC2B_V3B
R16
3
ADC2B_V4B
3.00k
4
ADC2B_V5B
5
ADC2B_V6B
6
ADC2B_V7B
AGND
ADC_AVDD
ADC2B_V2B
ADC2B_V7B
R36
R70
R65
10.5k
DNP
DNP
10.0k
0
V7B
R35
R69
10.5k
DNP
DNP
C27
10.0k
100nF
R37
3.00k
AGND
AGND
RCAPA
ADC_AVDD
1
3
JP1
TMP61_VBIAS
R32
ADC2A_V0A
DNP
R2
0
10.0k
R31
V_TMP61
0
R18
TMP6131QLPGMQ1
AGND
SBAU413 – OCTOBER 2022
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ADC2 inputs:
ADC2A_V3A
ADC2A_V5A
ADC_AVDD
Unipolar
R39
R51
ADC2y_V1y/2y
30.9k
13.7k
Gain = 1
0V to 10V
R40
R52
Bipolar
30.9k
13.7k
C16
ADC2y_V3y/4y
V1A
V3A
V5A
Gain = 4
-10V to +10V
R44
R56
100nF
C3
C12
1.96k
1.96k
AGND
ADC_IOVDD
100nF
100nF
Pseudo-diff
V7A
ADC2y_V5y/6y
Gain = 2
-8.5V to +10V
AGND
ADC2A_V4A
ADC2A_V6A
Default setting: [2-3]
R45
R58
30.9k
13.7k
To bypass internal LDOs, short [1-2] and
provide external voltage using terminal blocks.
R46
R59
30.9k
13.7k
C20
V2A
V4A
V6A
R50
R63
100nF
C10
C14
1.96k
1.96k
AGND
100nF
100nF
V7A
Vin = 0 V to 10 V
Default Gain = 4
AGND
R3
ADC3A_VPA
30.9k
ADC2B_V3B
ADC2B_V5B
R42
R54
ADC3A_VNA
30.9k
13.7k
R13
AGND
0
R41
R53
30.9k
13.7k
ADC1A_CPA
C17
V1B
V3B
V5B
R21
AGND
R43
R55
100nF
0
C4
C13
1.96k
1.96k
AGND
ADC1A_CNA
100nF
100nF
V7B
ADC1B_CPB
AGND
ADC1B_CNB
ADC2B_V4B
ADC2B_V6B
R22
AGND
R48
R61
0
30.9k
13.7k
R4
ADC3B_VPB
30.9k
R47
R60
30.9k
13.7k
C21
V2B
V4B
V6B
ADC3B_VNB
R14
R49
R64
100nF
C11
C15
AGND
1.96k
1.96k
AGND
0
100nF
100nF
V7B
Vin = 0 V to 10 V
Default Gain = 4
AGND
R5
ADC2B_V0B
DNP
U1
0
ADC_AVDD
R7
4
3
V0B
VDD
OUT
1.50k
C1
C2
10nF
1
100nF
GND
2
GND
V0A
5
GND
AGND
AGND
LMT84QDCKRQ1
C7
100nF
AGND
-40C to 150C = 1.247 V to 183 mV
AGND
Figure 7-7. Analog Inputs, ADC Power, and Interface Connections
Copyright © 2022 Texas Instruments Incorporated
ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
JP2
VADC_HV
ADC_APWR
ADC_APWR
ADC_AVDD
1
3
J6
J2
C23
C22
ANALOG ADC SUPPLY
1µF
1µF
ADC_APWR
AGND
AGND
AGND
JP3
VADC_HV
ADC_DPWR
ADC_DPWR
ADC_IOVDD
1
3
J8
C25
C28
AGND
1µF
1µF
DIGITAL ADC SUPPLY
ADC_DPWR
DGND
DGND
DGND
U2
38
ADC_APWR
APWR
37
ADC_DPWR
DPWR
R66
34
ADC_IOVDD
IO VDD
0.1
R57
40
ADC_AVDD
AVDD
TP1
0.1
VPA/GPIO0A
R12
R27
3
VPA/ GPI O0A
4
30.9k
0
VNA/ GPI O1A
R25
C8
GPIO2/F AULT
1.96k
2200pF
V0A
2
R28
V0A
GPIO3/ OCCA
V1A
1
V1A
GPIO4/ OCCB
V2A
48
0
V2A
TP5
V3A
47
V3A
VNA/GPIO1A
V4A
46
V4A
V5A
45
V5A
R19
V6A
44
V6A
V7A
100
43
V7A
R8
C5
100
0.047uF
5
CPA
R20
100
6
CNA
10
CPB
9
R24
100
CNB
R9
C6
100
0.047uF
V0B
11
V0B
R23
V1B
12
V1B
V2B
13
100
V2B
V3B
14
V3B
TP2
V4B
15
V4B
VPB/GPIO0B
V5B
16
R15
R30
V5B
V6B
17
V6B
V7B
18
30.9k
0
V7B
R26
C9
1.96k
2200pF
8
R29
VPB/G PI O0B
7
VNB/G PI O1B
0
TP6
VNB/GPIO1B
Thermal_ Pad
ADS131B26QPHPRQ1
TP3
TP4
TP7
TP9
AGND
DGND
ISO_GND
AGND
NT1
Net-Tie
DGND
ADC DIGITAL
28
SCLK
SCLK
30
SDI
SDI
29
SDO
SDO
31
CS
CS
ADC_DIGITAL
ADC_DIGITAL
27
DRDY
DRDY
23
RESET
RESET
ADC_IOVDD
33
GPIO0 / MHD
GPIO0/MHD
26
GPIO1
R73
GPIO1
25
100k
GPIO2/FAULT
24
GPIO3/OCCA
22
GPIO4/OCCB
CLK
R71
0
32
DNP
CLK
C24
DGND
R76
R74
R75
R77
R81
100k
100k
100k
100k
100k
36
DCAP
220nF
C18
DGND
41
RCAPA
DGND DGND DGND DGND DGND
RCAPA
1µF
C19
AGND
20
RCAPB
RCAPB
1µF
AGND
DCAP between pins 35-36
21
AGND
RCAPA between pins 41-42
39
AGND
RCAPB between pins 19-20
42
AGNDA
19
AGNDB
R72
R78
R79
R80
R82
100k
100k
100k
100k
100k
35
DGND
AGND
49
DGND
DGND DGND DGND DGND DGND
AGND
J7
ADC_DIGITAL.GPIO0/MHD
1
2
ADC_DIGITAL.GPIO0/MHD
ADC_DIGITAL.CS
3
4
ADC_DIGITAL.CS
ADC_DIGITAL.SDI
ADC_DIGITAL.SDI
5
6
ADC_DIGITAL.SDO
ADC_DIGITAL.SDO
7
8
ADC_DIGITAL.SCLK
ADC_DIGITAL.SCLK
9
10
ADC_DIGITAL.DRDY
ADC_DIGITAL.DRDY
11
12
ADC_DIGITAL.GPIO1
ADC_DIGITAL.GPIO1
13
14
ADC_DIGITAL.GPIO2/FAULT
ADC_DIGITAL.GPIO2/FAULT
15
16
ADC_DIGITAL.GPIO3/OCCA
ADC_DIGITAL.GPIO3/OCCA
17
18
ADC_DIGITAL.RESET
ADC_DIGITAL.RESET
19
20
ADC_DIGITAL.GPIO4/OCCB
21
22
ADC_DIGITAL.GPIO4/OCCB
23
24
DEBUG
DGND
DGND
ADS131B26Q1EVM-PDK Evaluation Module
29
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