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ADS131B26Q1EVM-PDK Software Reference
6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
Figure 6-3
displays the Channel Configurations register map page. These register controls allow the user to
configure the register settings for ADC1A, ADC1B, ADC3A, and ADC3B in a more user-friendly interface.
The page is partitioned into ADC1A and ADC3A settings on the left and ADC1B and ADC3B settings on the
right. At the top of each section are Global Settings for ADC1A and ADC3A and Global Settings for ADC1B
and ADC3B, which contain the register settings from addresses 82h and C2h, respectively.
Below the global channel settings are individual ADC controls to figure the following settings:
•
ADC enable
•
Channel gain
•
Channel Mux
•
Current Source or Sink Mux
•
Current Source or Sink Value
•
Offset Calibration
•
Gain Calibration
18
ADS131B26Q1EVM-PDK Evaluation Module
Figure 6-3. Channel Configurations Register Page
Copyright © 2022 Texas Instruments Incorporated
www.ti.com
SBAU413 – OCTOBER 2022
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