Digital Header; Clock Options; Figure 3-1. External Adc Clock Options (Schematic); Table 3-2. Debug Header Pins (J7) - Texas Instruments ADS131B26Q1EVM-PDK User Manual

Digital Interface

3.2 Digital Header

In addition to the PHI connector, header J7 on the EVM is connected to the digital inputs and outputs between
the ADS131B26-Q1 and the PHI connector. Each row is shorted across both pins to allow access to an external
logic analyzer or oscilloscope and an external controller simultaneously.

3.3 Clock Options

The ADS131B26-Q1 uses an internal oscillator by default after power-up. The internal oscillator frequency (f
has a nominal frequency of 8.192 MHz and serves as the primary timing reference for both analog and digital
circuitry inside the device. The ADC modulator frequency (f
f / 2) and controls the timing of the input sample-and-hold switches inside each delta-sigma ADC modulator.
CLK
In addition to the internal oscillator, the EVM allows the user to provide an external clock frequency to the ADC
CLK input pin. The external clock signal can either come from:
1. The onboard crystal oscillator (Y1), which has a nominal frequency of 8.192 MHz
2. An external clock source connected to the SMA connector (J10)
One advantage to using either external ADC clock option on the EVM is the ability to synchronize the DC/DC
converter switching frequency with a null in the ADC digital sinc3 filter. For more information, see
Figure 3-1 shows a schematic of the external clock options.
10 ADS131B26Q1EVM-PDK Evaluation Module

Table 3-2. DEBUG Header Pins (J7)

Signal Name
GPIO0/MHD
CSn
SDI
SDO
SCLK
DRDYn
GPIO1
GPIO2/FAULT
GPIO3/OCCA
RESETn
GPIO4/OCCB
DGND

Figure 3-1. External ADC Clock Options (Schematic)

Copyright © 2022 Texas Instruments Incorporated
Table 3-2 lists the digital header pins.
Digital Header Pins
J7[1-2]
J7[3-4]
J7[5-6]
J7[7-8]
J7[9-10]
J7[11-12]
J7[13-14]
J7[15-16]
J7[17-18]
J7[19-20]
J7[21-22]
J7[23-24]
) is equal to one-half the clock frequency (f
MOD
www.ti.com
)
CLK
=
MOD
Section 4.1.
SBAU413 – OCTOBER 2022
Submit Document Feedback