Emulation Timing Calculations - Texas Instruments TMS320C6000 Reference Manual

Emulation Timing Calculations

6 Emulation Timing Calculations
The following examples help you calculate emulation timings in your system.
For actual target timing parameters, see the appropriate device data sheets.
Assumptions:
Given in Table 2 (on page 7):
There are two key timing paths to consider in the emulation design:
-
-
Of the following two cases, the worst-case path delay is calculated to deter-
mine the maximum system test clock frequency.
Case 1: Single processor, direct connection, TMS/TDI timed from TCK_RET low.
t
pd TCK_RET–TMS TDI
In this case, the TCK_RET-to-TMS/TDI path is the limiting factor.
8 Designing for JTAG Emulation
t Target TMS/TDI setup to TCK high
su(TTMS)
t Target TDO delay from TCK low
d(TTDO)
t Target buffer delay, maximum
d(bufmax)
t Target buffer delay, minimum
d(bufmin)
t Target buffer skew between two devices
(bufskew)
in the same package:
[t
d(bufmax)
t Assume a 40/60 duty cycle clock
(TCKfactor)
t Emulator TMS/TDI delay from TCK_RET
d(TMSmax)
low, maximum
t TDO setup time to emulator TCK_RET
su(TDOmin)
high, minimum
The TCK_RET-to-TMS/TDI path, called t
The TCK_RET-to-TDO path, called t
t
d TMSmax
+
[ 20ns ) 10ns ]
+
+ 75ns ( 13.3 MHz )
t
d TTDO
+
t
pd TCK_RET–TDO
[ 15ns ) 3ns ]
+
0.4
+ 45ns ( 22.2 MHz )
] × 0.15
− t
d(bufmin)
pd(TCK_RET−TMS/TDI)
pd(TCK_RET−TDO)
) t
su TTMS
t
TCKfactor
0.4
) t
su TDOmin
t
TCKfactor
10 ns
15 ns
10 ns
1 ns
1.35 ns
0.4
(40%)
20 ns
3 ns
, and
.
SPRU641