Designing Your Target System's Emulator Connector (14-Pin Header) - Texas Instruments TMS320C6000 Reference Manual

This document assists you in meeting the design requirements of the
XDS510 emulator with respect to JTAG designs and discusses the XDS510
cable (manufacturing part number 2617698-0001). This cable is identified by
a label on the cable pod marked JTAG 3/5 V and supports both standard 3-volt
and 5-volt target system power inputs.
The term JTAG as used in this document refers to Texas Instruments scan-
based emulation, which is based on the IEEE 1149.1 standard.
1

Designing Your Target System's Emulator Connector (14-Pin Header)

JTAG target devices support emulation through a dedicated emulation port.
This port is a superset of the IEEE 1149.1 standard and is accessed by the
emulator. To communicate with the emulator, your target system must have
a 14-pin header (two rows of seven pins) with the connections that are shown
in Figure 1. Table 1 describes the emulation signals.
Figure 1. 14-Pin Header Signals and Header Dimensions
PD (V
TCK_RET
† While the corresponding female position on the cable connector is plugged to prevent improper connection, the cable lead for
pin 6 is present in the cable and is grounded, as shown in the schematics and wiring diagrams in this document.
SPRU641
Designing for JTAG Emulation
TMS 1 2 TRST
TDI 3 4 GND
) 5 6 no pin (key)
CC
TDO 7 8 GND
9 10 GND
TCK 11 12 GND
EMU0 13 14 EMU1
Header Dimensions:
Pin-to-pin spacing, 0.100 in. (X,Y)
†
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
Designing for JTAG Emulation 3