Texas Instruments TMS320C6000 Reference Manual page 32

Index
J
JTAG emulator
buffered signals 15
no signal buffering 14
pod interface 10
signal timings 11
timing parameters 11
N
notational conventions 3
P
protocol, bus 9
R
related documentation from Texas Instruments 3
run/stop operation 14
2 Designing for JTAG Emulation
S
scan path linkers
secondary JTAG scan chain to an SPL 21
suggested timings 27
scan paths, TBC emulation connections for JTAG
scan paths 29
signal descriptions, 14-pin header 8
signals
buffering for emulator connections 14
description, 14-pin header 8
timing 11
T
TBC emulation connections for n JTAG scan
paths 29
test clock 16
timing calculations 12, 22
trademarks 4
SPRU641