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3.
User notification: The BIOS will try to map out defective rows found during base
memory test but will end up in an infinite reset loop.
Upon reset, the above messages will display again on the LCD and will keep
repeating in an infinite loop.
User action:
1.
2.
3.
Error logging: The defective row/DIMM(s) found during this test case will be logged
to the SEL and reported on screen.
Extended memory test
The extended memory test takes effect after both the first row test and the base
memory test have passed. The Extended Memory Test will test the physical memory
above 2 GB to a maximum of the total installed memory. Any errors found will be
detected to the failing memory row and recorded into the CMOS history bits for
processing during the next reset. Since this occurs after system POST, the BIOS will
not reset the system. Instead, error messages will be displayed on the video screen.
There is a 2 GB fixed gap between the memory address 2 GB to 4 GB that is reserved
for PCI. This 2 GB of memory addresses, as seen by the processor, will not be tested.
User notification
There are two sets of messages associated with this test. The first occurs when the test
is being performed. The message is as follows:
XXXXX MB Total Memory Installed
XXXXX MB Configured
XXXXX MB Tested
Memory Errors Detected
Note: The "memory errors detected" message will appear only if extended memory
80
Hardware Maintenance Manual: xSeries 380
First row test encounters an SBE, base memory test encounters memory errors
and a bad CMOS checksum was seen by BIOS.
"First row test" –
"0064 MB" –
"BASE MEMORY TEST" –
"ERRORS IN MEMORY" –
"RESETTING SYSTEM" –
Use the out-of-band mechanism of reading System Event Log (Intel's Server
Management software, specifically DPC, can be used for this) to determine the
location of the row of defective DIMMs from the SELViewer Utility. Replace the
defective DIMMs. If you do not have out-of-band access to SEL, then remove all
DIMMs from the system and populate the system one row at a time.
Clear CMOS via the front panel or via clear CMOS jumper (see "Clearing the
CMOS register" on page 220 ) in order to clear previous defective DIMM history.
Power on the system to continue.
test finds errors.
displayed on the upper LCD line
displayed on the lower LCD line
displayed on the upper LCD line
displayed on the upper LCD line
displayed on the lower LCD line (prior to resetting)
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