Timing Errors During K7Z File Generation - Keysight M5200A Startup Manual

4 Troubleshooting and Safety information

4.4.3: Timing errors during k7z file generation

76
If you encounter timing closure errors during sandbox design compilation,
c h a n g e t h e
p l a c e _ d e s i g n
keysight_common_build.tcl file, located at C:\Program Files\Keysight\
M5200A\BSP\<GW-version>\scripts. See
The
place_design -directive
# AltSpreadLogic_medium
# AltSpreadLogic_high
# AltSpreadLogic_low
# ExtraNetDelay_low
# ExtraNetDelay_high
# Explore
After changing this option, close the PathWave FPGA interface and
relaunch the application for the changes to take effect.
Figure 37 Changing place_design -directive in the keysight_common_build.tcl file
- d i r e c t i v e
Figure 37.
options available are:
M5200A PXIe Digitizer Modules Startup Guide
o p t i o n s i n t h e