Chapter 8 - CB Fail Protection
External Trip A
External Trip A
IA< Start
IA< Start
ZCD IA<
CB Fail Alarm
CB Fail Alarm
External Trip A
External Trip A
Ext Prot Reset
Ext Prot Reset
Prot Reset & I<
Prot Reset & I<
I< Only
I< Only
CB Open & I<
CB Open & I<
Pole Dead A
Pole Dead A
External Trip B
External Trip B
IB< Start
IB< Start
ZCD IB<
CB Fail Alarm
CB Fail Alarm
External Trip B
External Trip B
Ext Prot Reset
Ext Prot Reset
Prot Reset & I<
Prot Reset & I<
I< Only
I< Only
CB Open & I<
CB Open & I<
Pole Dead B
Pole Dead B
External Trip C
External Trip C
IC< Start
IC< Start
ZCD IC<
CB Fail Alarm
CB Fail Alarm
External Trip C
External Trip C
Ext Prot Reset
Ext Prot Reset
Prot Reset & I<
Prot Reset & I<
I< Only
I< Only
CB Open & I<
CB Open & I<
Pole Dead C
Pole Dead C
Figure 91: Circuit Breaker Fail logic - single phase start
CB Fail 1 Status
Enabled
CBF3 PhStart
CBFExtPhAStart
CBFExtPhBStart
CBFExtPhCStart
CB Fail 2 Status
Enabled
CBF3 PhStart
CBFExtPhAStart
CBFExtPhBStart
CBFExtPhCStart
Figure 92: Circuit Breaker Fail Trip and Alarm
184
S
S
S
Q
Q
Q
R
R
R
D
D
D
1
&
S
S
S
Q
Q
Q
R
R
R
D
D
D
&
1
&
S
S
S
Q
Q
Q
R
R
R
D
D
D
1
&
S
S
S
Q
Q
Q
R
R
R
D
D
D
&
1
&
S
S
S
Q
Q
Q
R
R
R
D
D
D
1
&
S
S
S
Q
Q
Q
R
R
R
D
D
D
&
1
&
&
1
&
1
&
1
&
1
&
1
&
1
1
1
1
Note on SR Latches
All latches are reset dominant and are triggered on the positive edge. If
the edge occurs while the reset is active, the detection of the edge is
delayed until the reset becomes non -active.
1
1
P24xM
CBFExtPhAStart
CBFExtPhBStart
CBFExtPhCStart
V00657
Bfail1 Trip 3ph
1
CB Fail Alarm
Bfail2 Trip 3ph
V00676
P24xM-TM-EN-2.1