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GE P24NM manual available for free PDF download: Technical Manual
GE P24NM Technical Manual (600 pages)
Motor Protection IED
Brand:
GE
| Category:
Relays
| Size: 63.99 MB
Table of Contents
Table of Contents
3
Chapter 1 Introduction
25
Figure 135: TCS Scheme
25
Rear Serial Port
26
Figure 137: TCS Scheme
26
Chapter Overview
27
Cip
27
Foreword
28
Target Audience
28
Typographical Conventions
28
Cip
28
Figure 142: PSL for TCS Scheme
28
Nomenclature
29
Compliance
29
Cip
29
Product Scope
30
Ordering Options
30
Cip
30
Features and Functions
31
Protection Functions
31
Control Functions
32
Measurement Functions
32
Communication Functions
33
Logic Diagrams
34
Figure 1: Key to Logic Diagrams
35
Functional Overview
36
Figure 2: Functional Overview (P24DM)
36
Chapter 2 Safety Information
37
Chapter Overview
39
Health and Safety
40
Symbols
41
Installation, Commissioning and Servicing
42
Lifting Hazards
42
Electrical Hazards
42
UL/CSA/CUL Requirements
43
Fusing Requirements
43
Equipment Connections
44
Protection Class 1 Equipment Requirements
44
Pre-Energisation Checklist
45
Peripheral Circuitry
45
Upgrading/Servicing
47
Decommissioning and Disposal
48
Regulatory Compliance
49
EMC Compliance: 2014/30/EU
49
LVD Compliance: 2014/35/EU
49
R&TTE Compliance: 2014/53/EU
49
UL/CUL Compliance
49
ATEX Compliance: 2014/34/EU
49
Chapter 3 Hardware Design
51
Chapter Overview
53
Hardware Architecture
54
Memory and Real Time Clock
54
Figure 3: Hardware Design Overview
54
Mechanical Implementation
56
Housing Variants
56
Figure 4: Exploded View of IED
56
20TE Rear Panel
57
Figure 5: 20TE Rear Panel
57
Figure 6: 30TE Three-MIDOS Block Rear Panel
58
Figure 7: 30TE Two-MIDOS Block + Communications Rear Panel
58
40TE Rear Panel
59
Figure 8: 30TE Two-MIDOS Block + Blanking Plate
59
Figure 9: 40TE Three-MIDOS Block + Communications Rear Panel
59
Terminal Connections
60
I/O Options
60
Front Panel
61
20TE Front Panel
61
Figure 10: Front Panel (20TE)
61
30TE Front Panel
62
Figure 11: Front Panel (30TE)
62
40TE Front Panel
63
Keypad
63
Figure 12: Front Panel (40TE)
63
Liquid Crystal Display
64
USB Port
64
Fixed Function Leds
65
Function Keys
65
Programable Leds
65
Chapter 4 Software Design
67
Chapter Overview
69
Software Design Overview
70
Figure 13: Software Structure
70
System Level Software
71
Real Time Operating System
71
System Services Software
71
Self-Diagnostic Software
71
Startup Self-Testing
71
System Boot
71
System Level Software Initialisation
72
Platform Software Initialisation and Monitoring
72
Continuous Self-Testing
72
Platform Software
73
Record Logging
73
Settings Database
73
Interfaces
73
Protection and Control Functions
74
Acquisition of Samples
74
Frequency Tracking
74
Fourier Signal Processing
74
Programmable Scheme Logic
75
Event Recording
75
Figure 14: Frequency Response (Indicative Only)
75
Disturbance Recorder
76
Function Key Interface
76
Chapter 5 Configuration
77
Chapter Overview
79
Settings Application Software
80
Using the HMI Panel
81
Navigating the HMI Panel
82
Getting Started
82
Figure 15: Navigating the HMI
82
Default Display
83
Default Display Navigation
84
Figure 16: Default Display Navigation
84
Password Entry
85
Processing Alarms and Records
86
Menu Structure
86
Changing the Settings
87
Direct Access (the Hotkey Menu)
88
Setting Group Selection Using Hotkeys
88
Control Inputs
89
Circuit Breaker Control
89
Function Keys
90
Date and Time Configuration
92
Time Zone Compensation
92
Daylight Saving Time Compensation
92
Settings Group Selection
93
Chapter 6 Current Protection Functions
95
Chapter Overview
97
Thermal Overload Protection
98
Thermal Replica
99
Thermal Trip
100
Figure 17: Thermal Overload Protection Logic Diagram
101
Figure 18: Cooling Time Constant
101
User Programmable Curve for Thermal Overload Protection
102
Application Notes
102
Thermal Overload Setting Guidelines
102
Figure 19: Example of Settings
104
Figure 20: Thermal Curve Modification
106
Overcurrent Protection Principles
108
IDMT Characteristics
108
IEC 60255 IDMT Curves
109
European Standards
111
Figure 21: IEC 60255 IDMT Curves
111
North American Standards
112
IEC and IEEE Inverse Curves
114
Figure 22: IEC Standard and very Inverse Curves
114
Figure 23: IEC Extremely Inverse and IEEE Moderate Inverse Curves
114
Differences between the North American and European Standards
115
Programmable Curves
115
Principles of Implementation
115
Figure 24: IEEE very and Extremely Inverse Curves
115
Timer Hold Facility
116
Figure 25: Principle of Protection Function Implementation
116
Phase Overcurrent Protection
118
Phase Overcurrent Protection Implementation
118
Non-Directional Overcurrent Logic
119
Figure 26: Non-Directional Overcurrent Logic Diagram
119
Directional Element
120
Figure 27: Directional Trip Angles
121
Directional Overcurrent Logic
122
Application Notes
122
Short Circuit Protection
122
Figure 28: Directional Overcurrent Logic Diagram (Phase a Shown Only)
122
Figure 29: or Logic
123
Figure 30: and Logic
123
Figure 31: Definite Time Overcurrent Element
124
Current Setting Threshold Selection
125
Figure 32: Selecting the Current Threshold Setting
125
Negative Sequence Overcurrent Protection
126
Negative Sequence Overcurrent Protection Implementation
126
Non-Directional Negative Sequence Overcurrent Logic
127
Directional Element
127
Figure 33: Negative Sequence Overcurrent Logic - Non-Directional Operation
127
Directional Negative Sequence Overcurrent Logic
128
Phase Rotation
128
Figure 34: Negative Sequence Overcurrent Logic - Directional Operation
128
Application Notes
129
Negative Sequence Protection
129
Figure 35: Equivalent Circuits
129
Earth Fault Protection
133
Earth Fault Protection Elements
133
Non-Directional Earth Fault Logic
134
IDG Curve
134
Directional Element
135
Residual Voltage Polarisation
135
Figure 36: IDG Characteristic
135
Figure 37: Directional Angles
136
Negative Sequence Polarisation
137
Figure 38: Directional EF Logic with Neutral Voltage Polarization (Single Stage)
137
Application Notes
138
Setting Guidelines (Directional Element)
138
Figure 39: Directional Angles
138
Figure 40: *Directional Earth Fault Logic with Negative Sequence Polarisation (Single Stage)
138
Peterson Coil Earthed Systems
139
Figure 41: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing
139
Figure 42: Earth Fault in Petersen Coil Earthed System
140
Figure 43: Distribution of Currents During a Phase C Fault
140
Figure 44: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System
141
Figure 45: Zero Sequence Network Showing Residual Currents
141
Setting Guidelines (Compensated Networks)
142
Figure 46: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case with Resistance
142
Solidly Earthed System
143
Insulated System
144
Figure 47: Fuse Characteristic
144
Figure 48: Current Distribution in an Insulated System with C Phase Fault
145
Figure 49: Phasor Diagrams for Insulated System with C Phase Fault
146
Resistance Earthed Systems
147
High Resistance Earthing
147
Petersen Coil Earthed Systems
148
Figure 50: Directional Tripping Characteristic
148
Figure 51: Current Distribution in Petersen Coil Earthed System
149
Figure 52: Distribution of Currents During a C Phase to Earth Fault
150
Figure 53: Theoretical Case - no Resistance Present in XL or XC
150
Figure 54: Zero Sequence Network Showing Residual Currents
151
Figure 55: Practical Case:- Resistance Present in XL and XC
152
Operation of Sensitive Earth Fault Element
153
Sensitive Earth Fault Protection
154
SEF Protection Implementation
154
Non-Directional SEF Logic
154
Figure 56: Non-Directional SEF Logic
154
EPATR B Curve
155
Directional Element
155
Figure 57: EPATR B Characteristic Shown for TMS = 1.0
155
Wattmetric Characteristic
156
Figure 58: Resistive Components of Spill Current
156
Icos Phi / Isin Phi Characteristic
157
Figure 59: Operating Characteristic for Icos
157
Directional SEF Logic
158
Figure 60: Directional SEF with VN Polarisation (Single Stage)
158
Application Notes
159
Insulated Systems
159
Figure 61: Current Distribution in an Insulated System with C Phase Fault
159
Setting Guidelines (Insulated Systems)
160
Figure 62: Phasor Diagrams for Insulated System with C Phase Fault
160
Figure 63: Positioning of Core Balance Current Transformers
161
Cold Load Pickup
162
Implementation
162
CLP Logic
163
Application Notes
163
CLP for Resistive Loads
163
CLP for Motor Feeders
163
Figure 64: Cold Load Pickup Logic
163
CLP for Switch Onto Fault Conditions
164
Selective Logic
165
Selective Logic Implementation
165
Selective Logic Diagram
165
Figure 65: Selective Logic
165
Timer Setting Selection
166
Figure 66: Selecting the Timer Settings
166
Blocked Overcurrent Protection
167
Blocked Overcurrent Implementation
167
Blocked Overcurrent Logic
167
Blocked Earth Fault Logic
167
Figure 67: Blocked Overcurrent Logic
167
Application Notes
168
Busbar Blocking Scheme
168
Figure 68: Blocked Earth Fault Logic
168
Figure 69: Simple Busbar Blocking Scheme
168
Figure 70: Simple Busbar Blocking Scheme Characteristics
169
Second Harmonic Blocking
170
Second Harmonic Blocking Implementation
170
Second Harmonic Blocking Logic (POC Input)
171
Application Notes
171
Setting Guidelines
171
Figure 71: 2Nd Harmonic Blocking Logic (POC Input)
171
Stall Protection
172
Prolonged Start
172
Figure 72: Start Successful
172
Locked Rotor During Starting - (Stall Time < Start Time)
173
Figure 73: Locked Rotor Detection
173
Stall During Running
174
Momentary Reduction in System Voltage During Running
174
Reacceleration after a Reduction in System Voltage
174
Figure 74: Reacceleration Detection
174
Low Voltage Ride through Authorization
175
Figure 75: Adjustable Reacceleration Authorization - Voltage Restored Within the Set Time
175
Auto Re-Start Authorization Restoration Sequence
176
Figure 76: Adjustable Reacceleration Authorization - Voltage Restored after the Set Time
176
Figure 77: Automatic Restart Authorized- Voltage Restored Within the Set Time
177
Application Notes
178
Start/Stall Protection
178
Figure 78: Automatic Restart Failed- Voltage Restored after the Set Time
178
Excessive Start Time/Locked Rotor Protection - Stall Time > Start Time
179
Stall Protection (Stall While Running)
179
Excessive Start Time/Locked Rotor Protection - Stall Time < Start Time
180
Momentary Reduction in System Voltage During Running of the Motor
180
Low Voltage Protection (Reacceleration Authorization)
181
AUTO RE-START Authorization
181
Number of Starts
182
Figure 79: Start Inhibition Example 1
183
Time between Starts
184
Figure 80: Start Inhibition Example 2
184
Number of Starts Limitation
185
Figure 81: Time between Starts
185
Anti-Backspin Protection
186
Application Notes
187
Anti-Backspin Protection
187
Chapter 7 Restricted Earth Fault Protection
189
Chapter Overview
191
REF Protection Principles
192
Figure 83: REF Protection for Delta Connected Winding
192
Figure 84: REF Protection for Star Connected Winding
192
Restricted Earth Fault Types
193
Low Impedance Bias Characteristic
193
High Impedance REF Principle
194
Figure 85: Three-Slope REF Bias Characteristic
194
Figure 86: High Impedance REF Principle
194
Figure 87: High Impedance REF Connection
195
Restricted Earth Fault Protection Implementation
196
Restricted Earth Fault Protection Settings
196
Low Impedance REF
196
Setting the Bias Characteristic
196
Figure 88: REF Bias Characteristic
196
Delayed Bias
197
High Impedance REF
197
High Impedance REF Calculation Principles
197
Application Notes
199
Low Impedance REF Protection Application
199
Setting Guidelines for Biased Operation
199
Low Impedance REF Scaling Factor
199
Figure 89: Low Impedance REF Scaling Factor
199
High Impedance REF Protection Application
200
Setting Guidelines for High Impedance Operation
200
Chapter 8 CB Fail Protection
201
Chapter Overview
203
Circuit Breaker Fail Protection
204
Circuit Breaker Fail Implementation
205
Circuit Breaker Fail Timers
205
Zero Crossing Detection
205
Circuit Breaker Fail Logic
207
Figure 90: Circuit Breaker Fail Logic - Three Phase Start
207
Figure 91: Circuit Breaker Fail Logic - Single Phase Start
208
Figure 92: Circuit Breaker Fail Trip and Alarm
208
Undercurrent and ZCD Logic for CB Fail
209
Figure 93: Undercurrent and Zero Crossing Detection Logic for CB Fail
209
CB Fail SEF Protection Logic
210
Figure 94: CB Fail SEF Protection Logic
210
CB Fail Non Current Protection Logic
211
Figure 95: CB Fail Non Current Protection Logic
211
Circuit Breaker Mapping
212
Figure 96: Circuit Breaker Mapping
212
Application Notes
213
Reset Mechanisms for CB Fail Timers
213
Setting Guidelines (CB Fail Timer)
213
Setting Guidelines (Undercurrent)
214
Figure 97: CB Fail Timing
214
Chapter 9 Current Transformer Requirements
215
Chapter Overview
217
CT Requirements
218
Phase Overcurrent Protection
218
Directional Elements
218
Non-Directional Elements
219
Earth Fault Protection
219
Directional Elements
219
SEF Protection (Residually Connected)
219
Non-Directional Elements
220
SEF Protection (Core-Balanced CT)
220
Low Impedance REF Protection
220
High Impedance REF Protection
221
Use of Metrosil Non-Linear Resistors
221
Use of ANSI C-Class Cts
223
Chapter 10 Voltage Protection Functions
225
Chapter Overview
227
Undervoltage Protection
228
Undervoltage Protection Implementation
228
Undervoltage Protection Logic
229
Figure 98: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)
229
Application Notes
230
Undervoltage Protection
230
Overvoltage Protection
231
Overvoltage Protection Implementation
231
Overvoltage Protection Logic
232
Figure 99: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)
232
Application Notes
233
Overvoltage Setting Guidelines
233
Residual Overvoltage Protection
234
Residual Overvoltage Protection Implementation
234
Residual Overvoltage Logic
235
Application Notes
235
Calculation for Solidly Earthed Systems
235
Figure 100: Residual Overvoltage Logic
235
Calculation for Impedance Earthed Systems
236
Figure 101: Residual Voltage for a Solidly Earthed System
236
Setting Guidelines
237
Figure 102: Residual Voltage for an Impedance Earthed System
237
Negative Sequence Overvoltage Protection
238
Negative Sequence Overvoltage Implementation
238
Negative Sequence Overvoltage Logic
238
Application Notes
238
Setting Guidelines
238
Figure 103: Negative Sequence Overvoltage Logic
238
Positive Sequence Undervoltage Protection
240
Positive Sequence Undervoltage Implementation
240
Positive Sequence Undervoltage Logic
240
Figure 104: Positive Sequence Undervoltage Logic
240
Positive Sequence Overvoltage Protection
241
Positive Sequence Overvoltage Implementation
241
Positive Sequence Overvoltage Logic
241
Figure 105: Positive Sequence Overvoltage Logic
241
Moving Average Voltage Functions
242
Moving Average Undervoltage Logic
242
Figure 106: Moving Average Undervoltage Logic
242
Moving Average Overvoltage Logic
243
Moving Average Zero Sequence Voltage Logic
243
Figure 107: Moving Average Overvoltage Logic
243
Figure 108: Moving Average Zero Sequence Voltage Logic
243
Moving Average Positive Sequence Voltage Logic
244
Moving Average Negative Sequence Voltage Logic
244
Moving Average Undervoltage Blocking PSL
244
Figure 109: Moving Average Positive Sequence Voltage Logic
244
Figure 110: Moving Average Negative Sequence Voltage Logic
244
Figure 111: Average Voltage Protection Blocking
244
Chapter 11 Frequency Protection Functions
245
Chapter Overview
247
Frequency Protection Overview
248
Frequency Protection Implementation
248
Underfrequency Protection
249
Underfrequency Protection Implementation
249
Underfrequency Protection Logic
249
Application Notes
249
Setting Guidelines
249
Figure 112: Underfrequency Logic (Single Stage)
249
Overfrequency Protection
251
Overfrequency Protection Implementation
251
Overfrequency Protection Logic
251
Application Notes
251
Setting Guidelines
251
Figure 113: Overfrequency Logic (Single Stage)
251
Figure 114: Power System Segregation Based Upon Frequency Measurements
252
Independent R.O.C.O.F Protection
253
Indepenent R.O.C.O.F Protection Implementation
253
Independent R.O.C.O.F Protection Logic
253
Figure 115: Independent Rate of Change of Frequency Logic (Single Stage)
253
Application Notes
254
Setting Guidelines
254
Frequency-Supervised R.O.C.O.F Protection
255
Frequency-Supervised R.O.C.O.F Implementation
255
Frequency-Supervised R.O.C.O.F Logic
256
Application Notes
256
Frequency-Supervised R.O.C.O.F Example
256
Figure 116: Frequency-Supervised Rate of Change of Frequency Logic (Single Stage)
256
Setting Guidelines
257
Figure 117: Frequency Supervised Rate of Change of Frequency Protection
257
Average Rate of Change of Frequency Protection
258
Average R.O.C.O.F Protection Implementation
258
Figure 118: Average Rate of Change of Frequency Characteristic
258
Average R.O.C.O.F Logic
259
Application Notes
259
Setting Guidelines
259
Figure 119: Average Rate of Change of Frequency Logic (Single Stage)
259
Chapter 12 Power Protection Functions
261
Chapter Overview
263
Reverse Power Protection
264
Reverse Power Implementation
264
Chapter 13 Monitoring and Control
265
Chapter Overview
267
Event Records
268
Event Types
268
Opto-Input Events
269
Contact Events
269
Alarm Events
269
Fault Record Events
274
Security Events
274
Figure 120: Fault Recorder Stop Conditions
274
Maintenance Events
275
Protection Events
275
Platform Events
275
Disturbance Recorder
276
Measurements
277
Measured Quantities
277
Measured and Calculated Currents
277
Measured and Calculated Voltages
277
Power and Energy Quantities
277
Demand Values
278
Frequency Measurements
278
Other Measurements
278
Measurement Setup
278
Opto-Input Time Stamping
279
CB Condition Monitoring
280
Application Notes
280
Setting the Thresholds for the Total Broken Current
280
Setting the Thresholds for the Number of Operations
280
Setting the Thresholds for the Operating Time
281
Setting the Thresholds for Excesssive Fault Frequency
281
CB State Monitoring
282
CB State Monitoring Logic
283
Figure 121: CB State Monitoring Logic
283
Circuit Breaker Control
284
CB Control Using the IED Menu
284
CB Control Using the Hotkeys
285
CB Control Using the Function Keys
285
Figure 122: Hotkey Menu Navigation
285
CB Control Using the Opto-Inputs
286
Remote CB Control
286
Figure 123: Default Function Key PSL
286
CB Healthy Check
287
Figure 124: Remote Control of Circuit Breaker
287
CB Control Logic
288
Figure 125: CB Control Logic
288
Pole Dead Function
289
Pole Dead Logic
289
Figure 126: Pole Dead Logic
289
System Checks
290
System Checks Implementation
290
VT Connections
290
Voltage Monitoring
290
Switch Status and Control
291
Figure 127: Representation of Typical Feeder Bay
291
Switch Status Logic
292
Figure 128: Switch Status Logic
292
Switch Control Logic
293
Figure 129: Switch Control Logic
293
Chapter 14 Supervision
295
Chapter Overview
297
DC Supply Monitor
298
DC Supply Monitor Implementation
298
Figure 130: DC Supply Monitor Zones
298
DC Supply Monitor Logic
299
Figure 131: DC Supply Monitor Logic
299
Voltage Transformer Supervision
300
Loss of One or Two Phase Voltages
300
Loss of All Three Phase Voltages
300
Absence of All Three Phase Voltages on Line Energisation
300
VTS Implementation
301
VTS Logic
301
Figure 132: VTS Logic
302
VTS Acceleration Indication Logic
303
Figure 133: VTS Acceleration Indication Logic
303
Current Transformer Supervision
304
CTS Implementation
304
CTS Logic
304
Figure 134: CTS Logic Diagram
304
Application Notes
305
Setting Guidelines
305
Trip Circuit Supervision
306
Trip Circuit Supervision Scheme
306
Resistor Values
306
Psl for Tcs Scheme 1
307
Trip Circuit Supervision Scheme
307
Resistor Values
308
Psl for Tcs Scheme 2
308
Trip Circuit Supervision Scheme 3
309
Resistor Values
309
Figure 139: TCS Scheme 3
309
Psl for Tcs Scheme 3
310
Trip Circuit Supervision Scheme
310
Figure 140
310
Figure 141: TCS Scheme 4
310
Resistor Values
311
Figure 136: PSL for TCS Scheme
311
Figure 138: PSL for TCS Scheme
311
Chapter 15 Digital I/O and PSL Configuration
313
Chapter Overview
315
Configuring Digital Inputs and Outputs
316
Scheme Logic
317
Figure 143: Scheme Logic Interfaces
317
PSL Editor
318
PSL Schemes
318
PSL Scheme Version Control
318
Configuring the Opto-Inputs
319
Assigning the Output Relays
320
Fixed Function Leds
321
Trip LED Logic
321
Figure 144: Trip LED Logic
321
Configuring Programmable Leds
322
Function Keys
324
Control Inputs
325
Inter-PSL Inputs and Outputs
326
Chapter 16 Communications
327
Chapter Overview
329
Communication Interfaces
330
Serial Communication
331
Universal Serial Bus
331
EIA(RS)485 Bus
331
EIA(RS)485 Biasing Requirements
332
K-Bus
332
Figure 145: RS485 Biasing Circuit
332
Figure 146: Remote Communication Using K-Bus
333
Standard Ethernet Communication
334
Redundant Ethernet Communication
335
Supported Protocols
335
Parallel Redundancy Protocol
335
High-Availability Seamless Redundancy (HSR)
336
HSR Multicast Topology
336
Figure 147: IED Attached to Separate Lans
336
HSR Unicast Topology
337
Figure 148: HSR Multicast Topology
337
HSR Application in the Substation
338
Figure 149: HSR Unicast Topology
338
Rapid Spanning Tree Protocol
339
Figure 150: HSR Application in the Substation
339
Figure 151: IED Attached to Redundant Ethernet Star or Ring Circuit
339
Configuring IP Address
340
Data Protocols
341
Courier
341
Physical Connection and Link Layer
341
Courier Database
341
Settings Categories
342
Setting Changes
342
Event Extraction
342
Disturbance Record Extraction
344
Programmable Scheme Logic Settings
344
Time Synchronisation
344
Courier Configuration
344
Physical Connection and Link Layer
346
Initialisation
347
Time Synchronisation
347
Spontaneous Events
347
General Interrogation (GI)
347
Cyclic Measurements
347
Commands
347
Test Mode
347
Disturbance Records
348
Command/Monitor Blocking
348
IEC 60870-5-103 Configuration
348
Dnp
349
Physical Connection and Link Layer
349
Object 1 Binary Inputs
350
Object 10 Binary Outputs
350
Figure 152: Control Input Behaviour
350
Object 20 Binary Counters
351
Object 30 Analogue Input
351
Object 40 Analogue Output
351
Object 50 Time Synchronisation
351
DNP3 Device Profile
352
DNP3 Configuration
360
DNP3 Unsolicited Reporting
361
Modbus
361
Physical Connection and Link Layer
361
MODBUS Functions
361
Response Codes
362
Register Mapping
362
Event Extraction
363
Disturbance Record Extraction
364
Figure 153: Manual Selection of a Disturbance Record
366
Figure 154: Automatic Selection of Disturbance Record - Method 1
367
Figure 155: Automatic Selection of Disturbance Record - Method 2
368
Figure 156: Configuration File Extraction
369
Figure 157: Data File Extraction
370
Setting Changes
371
Password Protection
371
Protection and Disturbance Recorder Settings
371
Time Synchronisation
372
Power and Energy Measurement Data Formats
373
MODBUS Configuration
374
Iec 61850
375
Benefits of IEC 61850
375
IEC 61850 Interoperability
376
The IEC 61850 Data Model
376
Figure 158: Data Model Layers in IEC61850
376
IEC 61850 in Micom Ieds
377
IEC 61850 Data Model Implementation
377
IEC 61850 Communication Services Implementation
377
IEC 61850 Peer-To-Peer (GOOSE) Communications
378
Mapping GOOSE Messages to Virtual Inputs
378
Ethernet Functionality
378
IEC 61850 Configuration
379
Concurrent IEC 61850 and DNP3.0 Operation
380
Read Only Mode
382
Courier Protocol Blocking
382
IEC 61850 Protocol Blocking
383
Read-Only Settings
383
Read-Only DDB Signals
383
Time Synchronisation
384
Demodulated IRIG-B
384
Figure 159: GPS Satellite Timing Signal
384
Demodulated IRIG-B Implementation
385
Sntp
385
Time Synchronsiation Using the Communication Protocols
385
Chapter 17 Cyber-Security
387
Overview
389
The Need for Cyber-Security
390
Standards
391
NERC Compliance
391
Cip 002
392
Cip 007
393
Ieee 1686-2007
393
Cyber-Security Implementation
395
NERC-Compliant Display
395
Four-Level Access
396
Figure 160: Default Display Navigation
396
Blank Passwords
397
Password Rules
398
Access Level Ddbs
398
Enhanced Password Security
398
Password Strengthening
398
Password Validation
399
Password Blocking
399
Password Recovery
400
Entry of the Recovery Password
400
Password Encryption
401
Disabling Physical Ports
401
Disabling Logical Ports
401
Security Events Management
402
Logging out
404
Chapter 18 Installation
405
Chapter Overview
407
Handling the Goods
408
Receipt of the Goods
408
Unpacking the Goods
408
Storing the Goods
408
Dismantling the Goods
408
Mounting the Device
409
Flush Panel Mounting
409
Rack Mounting
409
Software Only
410
Figure 161: Rack Mounting of Products
410
Cables and Connectors
412
Terminal Blocks
412
Power Supply Connections
412
Figure 162: Midos Terminal Block
412
Earth Connnection
413
Current Transformers
413
Voltage Transformer Connections
413
Watchdog Connections
414
EIA(RS)485 and K-Bus Connections
414
IRIG-B Connection
414
Figure 163: Earth Link for Cable Screen
414
Opto-Input Connections
415
Output Relay Connections
415
Ethernet Metallic Connections
415
Ethernet Fibre Connections
415
USB Connection
415
Case Dimensions
416
Figure 164: 20TE Case Dimensions
416
Figure 165: 30TE Case Dimensions
417
Figure 166: 40TE Case Dimensions
418
Chapter 19 Commissioning Instructions
419
Chapter Overview
421
General Guidelines
422
Commissioning Test Menu
423
Opto I/P Status Cell (Opto-Input Status)
423
Relay O/P Status Cell (Relay Output Status)
423
Test Port Status Cell
423
Monitor Bit 1 to 8 Cells
423
Test Mode Cell
423
Test Pattern Cell
424
Contact Test Cell
424
Test Leds Cell
424
Test Autoreclose Cell
424
Red and Green LED Status Cells
424
Commissioning Equipment
426
Recommended Commissioning Equipment
426
Essential Commissioning Equipment
426
Advisory Test Equipment
427
Product Checks
428
Product Checks with the IED De-Energised
428
Visual Inspection
428
Insulation
429
External Wiring
429
Watchdog Contacts
429
Power Supply
429
Product Checks with the IED Energised
429
Watchdog Contacts
430
Test LCD
430
Date and Time
430
Test Leds
430
Test Alarm and Out-Of-Service Leds
431
Test Trip LED
431
Test User-Programmable Leds
431
Test Opto-Inputs
431
Test Output Relays
431
Test Serial Communication Port RP1
431
Figure 167: RP1 Physical Connection
432
Test Serial Communication Port RP2
433
Test Ethernet Communication
433
Test Current Inputs
433
Figure 168: Remote Communication Using K-Bus
433
Test Voltage Inputs
434
Setting Checks
436
Apply Application-Specific Settings
436
Transferring Settings from a Settings File
436
Entering Settings Using the HMI
436
Protection Timing Checks
438
Overcurrent Check
438
Connecting the Test Circuit
438
Performing the Test
438
Check the Operating Time
438
Onload Checks
440
Confirm Current Connections
440
Confirm Voltage Connections
440
On-Load Directional Test
441
Final Checks
442
Chapter 20 Maintenance and Troubleshooting
443
Chapter Overview
445
Maintenance
446
Maintenance Checks
446
Alarms
446
Opto-Isolators
446
Output Relays
446
Measurement Accuracy
446
Replacing the Unit
447
Cleaning
447
Troubleshooting
448
Self-Diagnostic Software
448
Power-Up Errors
448
Error Message or Code on Power-Up
448
Out of Service LED on at Power-Up
449
Error Code During Operation
449
Mal-Operation During Testing
450
Failure of Output Contacts
450
Failure of Opto-Inputs
450
Incorrect Analogue Signals
450
PSL Editor Troubleshooting
450
Diagram Reconstruction
451
PSL Version Check
451
Repair and Modification Procedure
451
Chapter 21 Technical Specifications
453
Chapter Overview
455
Interfaces
456
Front USB Port
456
Rear Serial Port 1
456
IRIG-B Port
456
Rear Ethernet Port Copper
457
Rear Ethernet Port - Fibre
457
100 Base Fx Receiver Characteristics
457
100 Base Fx Transmitter Characteristics
457
Performance of Current Protection Functions
458
Three-Phase Overcurrent Protection
458
Three-Phase Overcurrent Directional Parameters
458
Thermal Overload Protection
458
Earth Fault Protection
458
Earth Fault Directional Parameters
459
Sensitive Earth Fault Protection
459
SEF Directional Parameters
460
Restricted Earth Fault Protection
460
Negative Sequence Overcurrent Protection
460
NPSOC Directional Parameters
461
Stall Protection
461
Circuit Breaker Fail and Undercurrent Protection
461
Broken Conductor Protection
461
Selective Overcurrent Protection
461
Cold Load Pickup Protection
462
Performance of Voltage Protection Functions
463
Undervoltage Protection
463
Overvoltage Protection
463
Residual Overvoltage Protection
463
Negative Sequence Voltage Protection
463
Rate of Change of Voltage Protection
464
Performance of Frequency Protection Functions
465
Overfrequency Protection
465
Underfrequency Protection
465
Supervised Rate of Change of Frequency Protection
465
Independent Rate of Change of Frequency Protection
466
Average Rate of Change of Frequency Protection
466
Load Restoration
467
Anti-Backspin
467
Power Protection Functions
468
Reverse Power Protection
468
Performance of Monitoring and Control Functions
469
Voltage Transformer Supervision
469
Current Transformer Supervision
469
CB State and Condition Monitoring
469
PSL Timers
469
DC Supply Monitor
469
Measurements and Recording
471
General
471
Measured Operating Data
471
Disturbance Records
472
Event, Fault and Maintenance Records
472
Regulatory Compliance
473
EMC Compliance: 2014/30/EU
473
LVD Compliance: 2014/35/EU
473
R&TTE Compliance: 2014/53/EU
473
UL/CUL Compliance
473
ATEX Compliance: 2014/34/EU
473
Mechanical Specifications
475
Physical Parameters
475
Enclosure Protection
475
Mechanical Robustness
475
Transit Packaging Performance
475
Ratings
476
AC Measuring Inputs
476
Current Transformer Inputs
476
Voltage Transformer Inputs
476
Power Supply
477
Auxiliary Power Supply Voltage
477
Nominal Burden
477
Auxiliary Power Supply Interruption
477
Input / Output Connections
478
Isolated Digital Inputs
478
Nominal Pickup and Reset Thresholds
478
Standard Output Contacts
478
Watchdog Contacts
479
Shorting Link
479
Environmental Conditions
480
Ambient Temperature Range
480
Temperature Endurance Test
480
Ambient Humidity Range
480
Corrosive Environments
480
Type Tests
481
Insulation
481
Creepage Distances and Clearances
481
High Voltage (Dielectric) Withstand
481
Impulse Voltage Withstand Test
481
Electromagnetic Compatibility
483
Mhz Burst High Frequency Disturbance Test
483
Damped Oscillatory Test
483
Immunity to Electrostatic Discharge
483
Electrical Fast Transient or Burst Requirements
483
Surge Withstand Capability
483
Surge Immunity Test
484
Immunity to Radiated Electromagnetic Energy
484
Radiated Immunity from Digital Communications
484
Radiated Immunity from Digital Radio Telephones
484
Immunity to Conducted Disturbances Induced by Radio Frequency Fields
484
Magnetic Field Immunity
485
Conducted Emissions
485
Radiated Emissions
485
Power Frequency
485
Appendix A Ordering Options
487
Appendix B Settings and Signals
491
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