Rigol MSQ7054 User Manual page 333

Chapter 18 Store and Load
Threshold
Rx
Polarity
Endian
Data
Stop Bit
Parity
Package
Separator
I2C
Bus Status
Clock
SCL Thre
SDA
SDA Thre
Exchange
R/W
SPI
Bus Status
Mode
Timeout
CLK
Threshold
Slope
MISO
Threshold
MOSI
Polarity
Width
Endian
LIN
Bus Status
Source
Threshold
Baud
Parity
Version
CAN
Bus Status
Source
Threshold
Signal
Baud
Sample Position
MSO7000/DS7000 User Guide
0 V
OFF
LSB
8 bits
1 bit
None
OFF
0(NUL)
OFF
CH1
0 V
CH2
0 V
SCL/SDA
Without
OFF
Timeout
1 μs
CH1
0 V
Rising
CH2
0 V
OFF
8
MSB
OFF
CH1
0 V
19.2 kbps
Without
1.X
OFF
CH1
0 V
CAN_L
1 Mbps
50%
RIGOL
18-25