User Test I/O; Gtx Transceiver Pins - Xilinx ML623 User Manual

User Test I/O

[Figure
A standard 2 x 6, 100-mil pitch header (J197) brings out 6 FPGA I/O for test purposes.
Table 1-12
Table 1-12: User Test I/O

GTX Transceiver Pins

[Figure
All FPGA GTX transceiver pins are connected to differential SMA connector pairs. The
GTX transceivers are grouped into five sets of four (referred to as Quads) which share two
differential reference clock pin pairs
corresponding SMA connector are shown in
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
1-2, callout 17]
lists these pins.
FPGA Pin Net Name
U30 IO_L8N_SRCC_14_U30
U31 IO_L8P_SRCC_14_U31
D32 IO_L15N_16_D32
D31 IO_L15P_16_D31
K27 IO_L9N_MRCC_16_K27
K26 IO_L9P_MRCC_16_K26
1-2, callout 18]
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J197 Pin
2
4
6
8
10
12
(Figure 1-7). The transceiver pins and their
Table 1-13.
Detailed Description
21