Differential Sma Global Clock Inputs; Superclock-2 Module - Xilinx ML623 User Manual

Chapter 1: ML623 Board Features and Operation
Table 1-6: Single-Ended SMA Clock Connections

Differential SMA Global Clock Inputs

[Figure
The ML623 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA clock pins are
connected to the SMA connectors as shown in
Table 1-7: Differential SMA Clock Connections

SuperClock-2 Module

[Figure
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise clock source for the ML623 board. The clock module
maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1
reset pin.
The ML623 board also supplies 5V, 3.3V, and 2.5V input power to the clock module
interface.
Table 1-8: SuperClock-2 FPGA I/O Mapping
18
FPGA Pin Net Name
H28 CLK_A
K24 CLK_B
1-2, callout 12]
FPGA Pin Net Name
B31 CLK_DIFF_A_P
A31 CLK_DIFF_A_N
L23 CLK_DIFF_B_P
M22 CLK_DIFF_B_N
1-2, callout 13]
Table 1-8 shows the FPGA I/O mapping for the SuperClock-2 module interface.
FPGA Pin Net Name
J17 CM_LVDS1_P
J16 CM_LVDS1_N
K18 CM_LVDS2_P
K17 CM_LVDS2_N
E16 CM_LVDS3_P
D16 CM_LVDS3_N
A16 CM_GCLK_P
B16 CM_GCLK_N
C18 CM_CTRL_0
B18 CM_CTRL_1
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SMA Connector
J171
J172
Table 1-7.
SMA Connector
J167
J168
J169
J170
J32 Pin
1
3
9
11
17
19
25
27
61
63
ML623 Board User Guide
UG724 (v1.1) September 15, 2010