Xilinx ML623 User Manual page 10

Virtex-6 fpga gtx transceiver characterization board
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X-Ref Target - Figure 1-2
1a
1c
1e
1b
1f
1g
1f
1d
1a Main Power Switch (SW1)
1b 12V Mini-Fit connector (J122)
1c 12V ATX connector (J141)
1d Power regulation jumpers (J30, J31, J33, J102, J104, J105) 13
1e Regulation Inhibit (J14, J19)
1f
External power supply jacks
1g TI PMBus connector (J6)
1h GTX Transceiver power supply module
2
FPGA configuration connector (J1)
3
PROG push button, active Low (SW5)
4
DONE LED (DS6)
5
INIT LED (DS20)
6
System ACE controller (U25)
7
System ACE reset, active Low (SW2)
Configuration address DIP switch (SW3)
8
9
JTAG isolation jumpers (J22, J23, J195, J196)
Figure 1-2: Detailed Description of ML623 Board Components
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
1e
21b
www.xilinx.com
18
10
19
12
11
12
21a
21c
23
10
200 MHz 2.5V LVDS oscillator (U7)
11
Single-ended SMA global clock input (J171, J172)
12
Differential SMA global clock inputs (J167, J166, J169, J170)
SuperClock-2 module
14
User LEDs, active High (DS10 - DS17)
15
User DIP switches, active High (SW7)
16
User push buttons, active High (SW4, SW6)
17
User test I/O (J197)
18
GTX transceiver pins
19
GTX transceiver clock input SMAs
20
USB to UART bridge (U26)
21a FMC1 connector (J112)
21b FMC2 connector (J113)
21c FMC3 connector (J115)
22
System Monitor
2
23
I
C Bus Management (U27)
Detailed Description
4
5
9
7
20
3
8
6
2
1h
1f
13
17
22
16
15 14
UG724_c1_02_063010
9

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