Xilinx ML623 User Manual page 23

Virtex-6 fpga gtx transceiver characterization board
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Chapter 1: ML623 Board Features and Operation
X-Ref Target - Figure 1-7
Figure 1-7: GTX Transceiver and Reference Clock SMA Locations
Table 1-13: GTX Transceiver Pins
22
QUAD_113
QUAD_114
112 Clocks
113 Clocks
114 Clocks
QUAD_112
FPGA Pin
AP5
AP6
AP1
AP2
AM5
AM6
AN3
AN4
AL3
AL4
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QUAD_115
116 Clocks
115 Clocks
114 Clocks
Net Name
SMA Connector
112_RX0_P
112_RX0_N
112_TX0_P
112_TX0_N
112_RX1_P
112_RX1_N
112_TX1_P
112_TX1_N
112_RX2_P
112_RX2_N
QUAD_116
UG724_c1_07_040610
Trace Length (Mils)
J51
7,365
J52
7,361
J53
9,861
J54
9,853
J55
6,449
J56
6,438
J57
9,079
J58
9,089
J41
5,624
J42
5,634
ML623 Board User Guide
UG724 (v1.1) September 15, 2010

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