User Test I/O; Gth Transceivers And Reference Clocks - Xilinx ML628 User Manual

Chapter 1: ML628 Board Features and Operation
Table 1-15: User Push Buttons

User Test I/O

[Figure
A standard 2 x 6, 100-mil pitch header (J285) brings out 6 FPGA I/O for test purposes.
Table 1-16
Table 1-16: User Test I/O

GTH Transceivers and Reference Clocks

[Figure
The ML628 board provides access to all GTH transceiver and reference clock pins on the
FPGA as shown in
RX-TX "lanes." Four lanes are referred to as a "Quad."
Note:
24
FPGA Pin Net Name
A27 USER_PB1
B27 USER_PB2
1-2, callout 17]
lists these pins.
FPGA Pin Net Name
M26 USER_I0_1
N26 USER_I0_2
C28 USER_I0_3
C27 USER_I0_4
A29 USER_I0_5
A28 USER_I0_6
1-2, callout 19]
Figure 1-10. The GTH transceivers are grouped into six sets of four
Figure 1-10 is for reference only and might not reflect the current revision of the board.
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Reference
Designator
SW6
SW4
J285 Pin
2
4
6
8
10
12
ML628 Board User Guide
UG771 (v1.0.1) June 28, 2011