Xilinx ML623 User Manual page 25

Chapter 1: ML623 Board Features and Operation
Table 1-13: GTX Transceiver Pins (Cont'd)
24
FPGA Pin Net Name
T2 114_TX2_N
R3 114_RX3_P
R4 114_RX3_N
P1 114_TX3_P
P2 114_TX3_N
N3 115_RX0_P
N4 115_RX0_N
M1 115_TX0_P
M2 115_TX0_N
L3 115_RX1_P
L4 115_RX1_N
K1 115_TX1_P
K2 115_TX1_N
K5 115_RX2_P
K6 115_RX2_N
H1 115_TX2_P
H2 115_TX2_N
J3 115_RX3_P
J4 115_RX3_N
F1 115_TX3_P
F2 115_TX3_N
G3 116_RX0_P
G4 116_RX0_N
D1 116_TX0_P
D2 116_TX0_N
E3 116_RX1_P
E4 116_RX1_N
C3 116_TX1_P
C4 116_TX1_N
D5 116_RX2_P
D6 116_RX2_N
B1 116_TX2_P
B2 116_TX2_N
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SMA Connector Trace Length (Mils)
J97
J96
J95
J94
J93
J136
J135
J134
J133
J130
J128
J127
J126
J120
J121
J118
J117
J116
J114
J111
J110
J157
J155
J154
J153
J152
J151
J150
J149
J147
J146
J145
J144
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
4,625
5,068
5,075
5,614
5,619
6,166
6,172
6,678
6,676
7,150
7,156
7,640
7,650
6,957
6,964
7,669
7,665
7,397
7,387
7,626
7,634
8,171
8,181
8,113
8,111
9,019
9,028
9,203
9,198
9,536
9,548
10,015
10,018