Differential Sma Global Clock Inputs; Superclock-2 Module - Xilinx ML628 User Manual

To use these clock inputs, remove jumpers across AFX SEL headers J186 and J187.
Table 1-10: Single-Ended SMA Clock Connections

Differential SMA Global Clock Inputs

[Figure
The ML628 board provides two pairs of differential SMA transceiver clock inputs that can
be used for connecting to an external function generator. The FPGA clock pins are
connected to the SMA connectors as shown in
Table 1-11: Differential SMA Clock Connections

SuperClock-2 Module

[Figure
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise and low-jitter clock source for the ML628 board. The
clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock
pair, and 1 reset pin.
module interface. The ML628 board also supplies 5V, 3.3V, and 2.5V input power to the
clock module interface.
Table 1-12: SuperClock-2 FPGA I/O Mapping
ML628 Board User Guide
UG771 (v1.0.1) June 28, 2011
FPGA Pin Net Name
AP33
R31
1-2, callout 12]
FPGA Pin Net Name
AN33 CLK_DIFF_1_P
AP33 CLK_DIFF_1_N
J33 CLK_DIFF_2_P
H33 CLK_DIFF_2_N
1-2, callout 13]
Table 1-12
FPGA Pin Net Name
B35 CM_LVDS1_P
B36 CM_LVDS1_N
C12 CM_LVDS2_P
C11 CM_LVDS2_N
BC33 CM_LVDS3_P
BD33 CM_LVDS3_N
A23 CM_GCLK_P
A24 CM_GCLK_N
G26 CM_CTRL_0
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SMA Connector
CLK_1 J171
CLK_2 J172
Table 1-11.
SMA Connector
J167
J168
J169
J170
shows the FPGA I/O mapping for the SuperClock-2
J32 Pin
1
3
9
11
17
19
25
27
61
Detailed Description
21