Port 5; Block Diagram Of P50 To P53 - NEC UPD789426 Series User Manual

4.2.5 Port 5

This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in
1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be
specified by a mask option.
This port is set in the input mode when the RESET signal is input.
Figure 4-13 shows a block diagram of port 5.
RD
WR
PORT
Output latch
(P50 to P53)
WR
PM
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
90
CHAPTER 4 PORT FUNCTIONS
Figure 4-13. Block Diagram of P50 to P53
PM50 to PM53
User's Manual U15075EJ2V1UD
V
DD
Mask option resistor
Mask ROM version only.
For flash memory version,
a pull-up resistor is not
incorporated.
P50 to P53
N-ch