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(1)
Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 5-2. Format of Processor Clock Control Register
Symbol
<7>
6
5
PCC
MCC
0
0
MCC
0
Operation enabled
1
Operation disabled
CSS0
PCC1
At f
X
0
0
f
(0.2 s)
X
0
1
f
/2
2
X
1
0
f
/2 (61 s)
XT
1
1
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 5.3 (3) Subclock control
register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. f
:
Main system clock oscillation frequency (crystal/ceramic oscillation)
X
2. f
: Main system clock oscillation frequency (RC oscillation)
CC
3. f
: Subsystem clock oscillation frequency
XT
CPU clock (f
) × 2 indicates the minimum instruction execution time. The following table shows minimum
CPU
instruction execution time based on each setting value.
CSS0
PCC1
0.4
0
0
1.6
0
1
122
1
0
1
1
CHAPTER 5 CLOCK GENERATOR
4
3
2
1
0
0
0
PCC1
Control of main system clock oscillator operation
CPU clock (f
= 5.0 MHz operation, f
= 32.768 kHz operation
XT
µ
µ
(0.8 s)
µ
Minimum instruction execution time
At f
= 5.0 MHz operation,
X
f
= 32.768 kHz operation
XT
µ
s
µ
s
µ
s
User's Manual U15075EJ2V1UD
0
Address
After reset
0
FFFBH
02H
) selection
Note
CPU
At f
= 4.0 MHz operation, f
CC
µ
f
(0.25 s)
CC
µ
f
/2
2
(1.0 s)
CC
At f
CC
f
= 32.768 kHz operation
XT
µ
0.5
s
µ
2.0
s
R/W
R/W
= 32.768 kHz operation
XT
= 4.0 MHz operation,
105
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