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CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20
SI20/P25/
RxD20
SO20/P24/
TxD20
SS20/P22
SCK20/P23/
ASCK20
Note See Figure 12-2 for the configuration of the baud rate generator.
Figure 12-1. Block Diagram of Serial Interface 20
Serial operation mode
register 20 (CSIM20)
Reception buffer
register 20 (RXB20)
Reception shift
register 20 (RXS20)
Port mode
register (PM24)
Parity operation
Stop bit addition
4
Transmission data counter
Parity detection
SL20, CL20, PS200, PS201
Stop bit detection
Reception data counter
Reception enabled
Reception clock
Start bit
Detection clock
detection
CSIE20
CSCK20
Clock phase
control
Internal bus
Asynchronous serial interface
status register 20 (ASIS20)
PE20 FE20 OVE20
Switching of the first bit
Transmission shift
register 20 (TXS20)
Reception
shift clock
Data phase
control
Transmission
and reception
clock control
Reception detected
TPS203 TPS202 TPS201 TPS200
Internal clock output
Baud rate generator
control register 20 (BRGC20)
External clock input
Internal bus
Asynchronous serial interface
mode register 20 (ASIM20)
TXE20 RXE20 PS201 PS200 CL20 SL20
Transmission
shift clock
Selector
CSIE20
DAP20
INTST20
INTSR20/INTCSI20
CSIE20
Baud rate
Note
generator
CSCK20
8
f
/2 to f
/2
X
X
4
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