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CHAPTER 3 CPU ARCHITECTURE ......................................................................................................46
3.1
Memory Space............................................................................................................................46
3.1.1
Internal program memory space ................................................................................................... 52
3.1.2
Internal data memory (internal high-speed RAM) space ............................................................... 53
3.1.3
Special function register (SFR) area ............................................................................................. 53
3.1.4
Data memory addressing .............................................................................................................. 54
3.2
Processor Registers ..................................................................................................................60
3.2.1
Control registers............................................................................................................................ 60
3.2.2
General-purpose registers............................................................................................................. 63
3.2.3
Special function registers (SFRs).................................................................................................. 64
3.3
Instruction Address Addressing ..............................................................................................67
3.3.1
Relative addressing....................................................................................................................... 67
3.3.2
Immediate addressing ................................................................................................................... 68
3.3.3
Table indirect addressing .............................................................................................................. 69
3.3.4
Register addressing ...................................................................................................................... 69
3.4
Operand Address Addressing ..................................................................................................70
3.4.1
Direct addressing .......................................................................................................................... 70
3.4.2
Short direct addressing ................................................................................................................. 71
3.4.3
Special function register (SFR) addressing ................................................................................... 72
3.4.4
Register addressing ...................................................................................................................... 73
3.4.5
Register indirect addressing.......................................................................................................... 74
3.4.6
Based addressing ......................................................................................................................... 75
3.4.7
Stack addressing........................................................................................................................... 75
CHAPTER 4 PORT FUNCTIONS ...........................................................................................................76
4.1
Port Functions............................................................................................................................76
4.2
Port Configuration .....................................................................................................................79
4.2.1
Port 0 ............................................................................................................................................ 80
4.2.2
Port 1 ............................................................................................................................................ 81
4.2.3
Port 2 ............................................................................................................................................ 82
4.2.4
Port 3 ............................................................................................................................................ 88
4.2.5
Port 5 ............................................................................................................................................ 90
4.2.6
Port 6 ............................................................................................................................................ 91
4.2.7
Port 7 ............................................................................................................................................ 92
4.2.8
Port 8 (
4.2.9
4.3
Registers Controlling Port Function ........................................................................................95
4.4
Port Function Operation..........................................................................................................101
4.4.1
Writing to I/O port ........................................................................................................................ 101
4.4.2
Reading from I/O port.................................................................................................................. 101
4.4.3
Arithmetic operation of I/O port ................................................................................................... 101
CHAPTER 5 CLOCK GENERATOR ....................................................................................................102
5.1
Clock Generator Functions.....................................................................................................102
12
µ
PD789426, 789436 Subseries only) ................................................................................ 93
µ
PD789426, 789436 Subseries only) ................................................................................ 94
User's Manual U15075EJ2V1UD
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