NEC UPD789426 Series User Manual page 141

Figure 7-3. Block Diagram of Output Controller (Timer 60)
TOE60 TOE61
F/F
(1) 8-bit compare register 50 (CR50)
This 8-bit register is used to continually compare the value set to CR50 with the count value in 8-bit timer
counter 50 (TM50) and to generate an interrupt request (INTTM50) when a match occurs.
CR50 is set with an 8-bit memory manipulation instruction.
RESET input makes CR50 undefined.
Cautions 1. If the CR50 is overwritten during timer operation in the PWM output mode (TMD501 = 1,
TMD500 = 0), a high level may be output for 1 cycle immediately after. If this waveform
poses a problem for the application, either <1> stop the timer when overwriting the
CR50, or <2> overwrite the CR50 with the TOE50 in a cleared status.
2. If the valid edge of the count clock is selected for both edges in the PWM output mode
(TEG50 = 1), do not set 00H, 01H, and FFH to the CR50. If the rising edge is selected
(TEG50 = 0), do not set 00H to CR50.
(2) 8-bit compare register 60 (CR60)
This 8-bit register is used to continually compare the value set to CR60 with the count value in 8-bit timer
counter 60 (TM60) and to generate an interrupt request (INTTM60) when a match occurs. When connected
to TM50 via a cascade connection and used as a 16-bit timer/event counter, the interrupt request (INTTM60)
occurs only when matches occur simultaneously between CR50 and TM50 and between CR60 and TM60
(INTTM50 does not occur).
CR60 is set with an 8-bit memory manipulation instruction.
RESET input makes CR60 undefined.
(3) 8-bit compare register H60 (CRH60)
In PWM output mode, the high-level width of timer output is set by writing a value to CRH60.
CRH60 is set with an 8-bit memory manipulation instruction.
RESET input makes CRH60 undefined.
CHAPTER 7 8-BIT TIMERS 50, 60
P32 P33
PM32
Output latch
Output latch
User's Manual U15075EJ2V1UD
PM33
TO60/P32/
INTP2
TO61/P33/
INTP3
Timer 60 output signal
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