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Symbol
<7>
<6>
TMC50
TCE50
TEG50
TCE50
0
Clears TM50 count value and stops operation
1
Starts count operation
TEG50
0
Counts at the rising edge of the count clock
1
Counts at both edges of the count clock
TCL502
TCL501
0
0
0
0
0
1
0
1
1
0
1
0
Other than above
TMD501
TMD500
0
0
0
1
0
0
0
0
1
0
1
0
Other than above
TOE50
0
Output disabled
1
Output enabled
CHAPTER 7 8-BIT TIMERS 50, 60
Figure 7-4. Format of 8-Bit Timer Mode Control Register 50
5
4
3
TCL502
TCL501
TCL500
Control of TM50 count operation
Valid edge selection for TM50 count clock
Note 2
TCL500
0
f
(5.0 MHz)
X
3
1
f
/2
(625 kHz)
X
7
f
/2
(39.1 kHz)
0
X
1
f
(32.768 kHz)
XT
0
Timer 60 match signal
1
Carrier clock (in carrier generator mode) or timer 60 output signal (in a mode other than
carrier generator mode)
Setting prohibited
TMD601
TMD600
0
0
Discrete mode (8-bit timer counter mode)
0
1
Cascade connection mode (16-bit timer counter mode)
1
1
Carrier generator mode
1
0
Timer 50: Discrete mode (8-bit counter mode)
Timer 60: PWM pulse generator mode
1
0
Timer 50: PWM free-running mode
Timer 60: PWM pulse generator mode
0
0
Timer 50: PWM free-running mode
Timer 60: Discrete mode (8-bit counter mode)
Setting prohibited
User's Manual U15075EJ2V1UD
2
1
<0>
TMD501
TMD500
TOE50
Note 1
Selection of timer 50 count clock
Selection of operation mode for timer 50 and timer 60
Control of timer output
Address
After reset
R/W
FF4DH
00H
R/W
Note 3
145
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