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(3)
Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Symbol
7
6
5
CSS
0
0
CLS CSS0
CLS
0
Operation based on the output of the (divided) main system clock
1
Operation based on the subsystem clock
CSS0
0
(Divided) output from the main system clock oscillator
1
Output from the subsystem clock oscillator
Note Bit 5 is read only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
CHAPTER 5 CLOCK GENERATOR
Figure 5-4. Format of Subclock Control Register
4
3
2
1
0
0
0
0
0
CPU clock operation status
Selection of the main system or subsystem clock oscillator
User's Manual U15075EJ2V1UD
Address
After reset
R/W
FFF2H
00H
R/W
Note
107
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