NEC UPD789426 Series User Manual page 320

DC Characteristics (T = –40 to +85°C, V
A
Parameter Symbol
Input leakage current, I
LIH1
high
I
LIH2
I
LIH3
Input leakage current, I
LIL1
low
I
LIL2
I
LIL3
Output leakage current, I
LOH
high
Output leakage current, I
LOL
low
Software pull-up R
1
resistor
Mask option pull-up R
2
Note 3
resistor
µ
Notes 1. PD789425, 789426, 789435, 789436, and 78F9436 only
2. If there is no on-chip pull-up resistor for P50 to P53 (specified by the mask option), if P50 to P53 have
been set to input mode when a read instruction is executed to read from P50 to P53, a low-level input
leakage current of up to –30
current is –3
3. Mask ROM products only
Remarks 1. Unless otherwise specified, the characteristics of alternate-function pins are the same as those of
port pins.
2. The items in parentheses apply when RC oscillation is selected (mask option).
CHAPTER 20 ELECTRICAL SPECIFICATIONS
= 1.8 to 5.5 V)
DD
Conditions
V = V
I DD
V = 12 V
I
V = 0 V
I
V = V
O DD
V = 0 V
O
V = 0 V
I
V = 0 V
I
µ
A flows during only one cycle. At all other times, the maximum leakage
µ
A.
User's Manual U15075EJ2V1UD
MIN.
P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P60 to P65, P70 to P72,
Note 1 Note 1
P80 , P81 , P90 to
Note 1
P97 , RESET
X1 (CL1), X2 (CL2), XT1,
XT2
P50 to P53
(N-ch open drain)
P00 to P03, P10, P11,
P20 to P26, P30 to P33,
P60 to P65, P70 to P72,
Note 1 Note 1
P80 , P81 , P90 to
Note 1
P97 , RESET
X1 (CL1), X2 (CL2), XT1,
XT2
P50 to P53
(N-ch open drain)
P00 to P03, P10, P11,
P20 to P26, P30 to P33,
Note 1
P70 to P72, P80 ,
Note 1 Note 1
P81 , P90 to P97
P50 to P53
TYP. MAX.
3
20
20
–3
–20
Note 2
–3
3
–3
50 100 200
10 30 60
Unit
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
kΩ
kΩ
321