Table 3-3. Boot Select Switch Table - S3 - Texas Instruments C2000 F28003x Series User Manual

Launchpad

Hide thumbs

Table Of Contents

Table of Contents

Hardware Description

Two blue LEDs, LED2 and LED3, are connected to the XDS110 debug probe. These indicate debugger activity

and are not controllable by any application software.

3.1.4 Encoder Connectors

The F28003x LaunchPad includes two headers, J12 and J13, which are used for connecting linear or rotary

incremental encoders. These headers take 5 V input signals that are stepped down to 3.3 V and wired to the

F280039C MCU. These signals are connected to the eQEP modules on the device when switch S5 is set

appropriately, see

Table

3-5. Each header has the EQEPA, EQEPB, and EQEPI signals available for each eQEP

module (1 and 2) as well as pins for GND and 5 V.

3.1.5 FSI

The F28003x MCU features the Fast Serial Interface (FSI) communications peripheral. The FSI enables robust

high-speed communications and is intended to increase the amount of information transmitted while reducing the

cost to communicate over an isolation barrier. The FSI signals TXCLK, TXD0, TXD1, RXCLK, RXD0, and RXD1

are available on J11. This header is set up in such a way that adding jumpers on the pins will connect the TX to

RX channels for external loopback and evaluation. Additionally, there are two GND signals on the connector that

can be used for a wrapped-pair connection to an external board with FSI. The GPIOs connected to this header

are only routed to the J11 FSI connector on this board, they are not routed to the boosterpack headers.

The LAUNCHXL-F280039C does not include any on-board isolation devices for the FSI signals. If interested

in evaluating the FSI peripheral with isolation devices, or differential drivers/receivers, please see the

TMDSFSIADAPEVM

plug on board.

3.1.6 CAN

The F28003x LaunchPad includes a connector (J14) for a CAN network. GPIO4 and GPIO5 are routed from the

F280039CPNS to J14 through the on-board CAN Transceiver. Both standard CAN and CAN-FD Mux options

exist on these F28003x device pins. Switch S4 is used to route GPIO4 and GPIO5 to either the CAN transceiver

and connector or the boosterpack headers. For more details, see

3.1.7 CLB

The configurable logic block (CLB) is a collection of blocks that can be interconnected using software to

implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance

existing peripherals through a set of interconnections, which provide a high level of connectivity to existing

control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules (eCAP), and

enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be connected to

other internal peripheral signals of the device or external GPIO pins. In this way, the CLB can be configured

to perform small logical functions to augment device peripheral inputs and outputs. Through the CLB, functions

that would otherwise be accomplished using external logic devices, such as FPGAs or CPLDs, can now be

implemented inside the C2000 MCU.

For more information on the CLB see the

3.1.8 Boot Modes

The F280039C boot ROM contains bootloading software that executes every time the device is powered on

or reset. Two pins, GPIO24 and GPIO32, are wired to the Boot Select switch (S3). By default, both pins are

set HIGH (1) so the device will boot from Flash. For more information on the F28003x boot modes, see the

TMS320F28003x Real-Time Microcontrollers Data

Boot Mode

Boot from Parallel GPIO

Boot from SCI / Wait boot

Boot from CAN

Boot from Flash (default)

™

C2000

F28003x Series LaunchPad

C2000™ Configurable Logic Block (CLB) training

Sheet.