Soc Boot Mode Switch Settings - Texas Instruments DRA72 Series User Manual

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3.5.4 MicroSD Card Cage
For non-volatile storage expansion, the EVM includes a microSD card cage. The cage is connected to the
MMC1 port of the SoC. To support higher-speed cards that operate at lower voltages, the IO supply is
changed from 3v3 to 1v8 through the PMIC LDO configuration (see the PMIC data manual for instructions
on how to change the voltage level). The SD card power can be cycled using the IO expander (EXP2,
PP5). For specific information regarding supported card types, densities, and speeds, see the device-
specific data manual for SoC.
Booting from the microSD card cage is supported on the EVM. No configuration is required, as the SD
card is selected by default. Ensure the correct SoC boot mode is set using the SYS_BOOT switches
(SW2, SW3).
3.5.5 GPMC NOR Flash Memory
A 512-Mbit NOR flash memory (x16) is supported as a non-volatile memory option on the EVM. It is
supported on chip select CS0, and thus can also be used as a boot device. To access, the onboard mux
must be enabled by setting SW5.p2 to ON. For booting, ensure the correct SoC boot mode is selected
using the SYS_BOOT switches (SW2, SW3).
NOR device used: Spansion S29GL512S10TFI010
3.5.6 GPMC NAND Flash Memory
A 2-Gbit NAND flash memory (x16) is supported as a non-volatile memory option on the EVM. It is
supported on chip select CS0, and thus can also be used as a boot device. To access, the onboard mux
must be enabled by setting SW5.p1 to ON. For booting, ensure the correct SoC boot mode is selected
using the SYS_BOOT switches (SW2, SW3).
NAND device used: Micron MT29F2G16AADWP:D
3.6 Boot Modes
The SoC supports a variety of different boot modes, determined by the 16-bit system boot setting present
on the shared specific I/O balls during the power-on sequence (see the TRM for details). Boot mode
selection is accomplished by setting the DIP switches SW2 and SW3 as shown in
cycling of power.
These SoC resources can be redeployed to support alternate interfaces after boot-up, by way of both SoC
and EVM mux settings.
An ON setting selects a logic 1 for the signals, and an OFF setting selects a logic 0.
SoC Interface (Internal System
Boot Input)
GPMC_AD0 (sysboot0)
GPMC_AD1 (sysboot1)
GPMC_AD2 (sysboot2)
GPMC_AD3 (sysboot3)
GPMC_AD4 (sysboot4)
GPMC_AD5 (sysboot5)
GPMC_AD6 (sysboot6)
GPMC_AD7 (sysboot7)
GPMC_AD8 (sysboot8)
GPMC_AD9 (sysboot9)
GPMC_AD10 (sysboot10)
GPMC_AD11 (sysboot11)
GPMC_AD12 (sysboot12)
GPMC_AD13 (sysboot13)
SPRUIB9 – December 2016
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Table 10. SoC Boot Mode Switch Settings
DIP Switch Ref Des. Position #
CPU Bd Net
GPMC_D00
GPMC_D01
GPMC_D02
GPMC_D03
GPMC_D04
GPMC_D05
GPMC_D06
GPMC_D07
GPMC_D08
GPMC_D09
GPMC_D10
GPMC_D11
GPMC_D12
GPMC_D13
Copyright © 2016, Texas Instruments Incorporated
Table
Connections
SW2.P1
SW2.P2
SW2.P3
SW2.P4
SW2.P5
SW2.P6
SW2.P7
SW2.P8
SW3.P1
SW3.P2
SW3.P3
SW3.P4
SW3.P5
SW3.P6
DRA72x EVM CPU Board User's Guide
Hardware
10, prior to
Factory Settings
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
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