Texas Instruments ADS1x48EVM User Manual page 3

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Figure 1-1. ADS1x48EVM Functional Block Diagram.................................................................................................................
Figure 2-1. Connecting the ADS1x48EVM to the PAMB
Figure 3-1. LED Indicators D1 and
Figure 3-2. Jumper (JP1) Selects AVDD on the ADS1x48EVM..................................................................................................
Figure 3-3. ADS1x48EVM VREF Options (Yellow) and Test Points (Red)..................................................................................
Figure 3-4. ADC Clock Options on the ADS1x48EVM..............................................................................................................
Figure 3-5. ADS1x48EVM-to-PAMBoard Connections..............................................................................................................
Figure 3-6. ADS1x48EVM Analog Input Terminal Blocks (J5, Left; J6,
Figure 3-7. Thermocouple Input Structure on the
Figure 3-8. Using REF5025 (input J5:3) to Bias a Thermocouple.............................................................................................
Figure 3-9. Thermistor Input Structure on the
Figure 3-10. Connecting a Thermistor to the J5 Terminal Block on the
Figure 3-11. PCB Layout for J5 Terminal Block Showing Copper Pours for CJC Measurement...............................................
Figure 3-12. RTD Input Structure on the
Figure 3-13. Connection Diagram for a 2-Wire RTD Using a Low-Side R
Figure 3-14. Connection Diagram for a 2-Wire RTD Using a High-Side R
Figure 3-15. Connection Diagram for a 3-Wire RTD Using One IDAC and a Low-Side R
Figure 3-16. Connection Diagram for a 3-Wire RTD Using One IDAC and a High-Side R
Figure 3-17. Connection Diagram for a 3-Wire RTD Using Two IDACs and a Low-Side R
Figure 3-18. Connection Diagram for a 3-Wire RTD Using Two IDACs and a High-Side R
Figure 3-19. Connection Diagram for a 4-Wire RTD Using a Low-Side R
Figure 3-20. Connection Diagram for a 4-Wire RTD Using a High-Side R
Figure 3-21. Using the TC± Inputs on J5 as General-Purpose Signal
Figure 4-1. Browser Extension and TI Cloud Agent Installation................................................................................................
Figure 4-2. ADS1x48EVM GUI Home Page..............................................................................................................................
Figure 4-3. Connected Hardware Information...........................................................................................................................
Figure 4-4. File Menu.................................................................................................................................................................30
Figure 4-5. Data Capture Window.............................................................................................................................................
Figure 4-6. Capture Settings
Figure 4-7. Capture Statistics....................................................................................................................................................
Figure 4-8. Time Domain Plot....................................................................................................................................................
Figure 4-9. Histogram Plot.........................................................................................................................................................33
Figure 4-10. Register Map.........................................................................................................................................................
Figure 4-11. Register Read and Write Controls.........................................................................................................................
Figure 4-12. Auto Read Options................................................................................................................................................
Figure 4-13. Register Write Options..........................................................................................................................................
Figure 5-1. Composite PCB Layout...........................................................................................................................................
Figure 5-2. Top Silkscreen.........................................................................................................................................................
Figure 5-3. Top Layer.................................................................................................................................................................39
Figure 5-4. Internal Ground Layer 1..........................................................................................................................................
Figure 5-5. Internal Ground Layer 2..........................................................................................................................................
Figure 5-6. Bottom Layer...........................................................................................................................................................
Figure 5-7. Bottom Silkscreen...................................................................................................................................................
Figure 5-8. ADS1x48EVM Schematic........................................................................................................................................41
SBAU378A - SEPTEMBER 2021 - REVISED JANUARY 2022
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List of Figures
Board...................................................................................................6
D5.........................................................................................................................................7
ADS1x48EVM..............................................................................................13
ADS1x48EVM....................................................................................................15
ADS1x48EVM............................................................................................................17
Slide-Out......................................................................................................................................31
Copyright © 2022 Texas Instruments Incorporated
Right)...........................................................................12
ADS1x48EVM.............................................................15
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REF
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REF
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REF
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REF
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REF
Inputs............................................................................27
ADS1x48EVM Evaluation Module
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