Clock I/O Pins - Renesas RX Family Application Note

RX Family

2.4 Clock I/O Pins

The wiring traces for the clock I/O pins (EXATL, XTAL, XCIN, and XCOUT) should be as short as possible,
including peripheral circuits. Shield the wiring pattern for the clock I/O pins with the GND pattern and do not
arrange the traces for the clock I/O pins in parallel with or across other traces (traces with large current flows
or rapid level changes). The GND traces used for shielding should be at least 0.3 mm wide and there should
be a space of 0.3 mm to 2.0 mm between them and adjacent traces. In addition, do not place the GND wiring
pattern and power supply wiring pattern in layers under a peripheral circuit incorporating a crystal oscillator.
Refer to the application notes below for information on crystal oscillators with low load capacitance (low-C
crystal oscillators). The latest versions and guides to new products can be downloaded from the Renesas
Electronics website.
• RX200 Series: Design Guide for Sub-Clock Circuits (R01AN1012EJ)
• RX600, RX700 Series: Design Guide for Sub-Clock Circuits (R01AN1187EJ)
Board design hint
If noise impinges on the clock I/O pins, the clock waveforms may become distorted, possibly causing
an MCU malfunction or program runaway. In addition, accurate clock signals cannot be input to the
MCU if there is a potential difference between the VSS inputs to the MCU and oscillators.
Figure 2.12 shows an example clock I/O pin circuit configuration.
Contact the oscillator
manufacturer for information
on load capacitance.
R01AN1411EJ0110 Rev.1.10
Oct.26.21
Figure 2.12 Example Clock I/O Pin Circuit Configuration
Hardware Design Guide
XTAL
XCIN
RX Family MCU
EXTAL
XCOUT
VSS
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