Sram - Renesas REG10J0052-0200 User Manual

4.4.SRAM

The board is provided with 512 kilobytes of static RAM arranged as 256k x 16 bit words.
This RAM is byte addressable, provided the host RSK supports this.
The chip select used for the RAM is CS3 which is on JA3 pin 45.
Please note the timing. This will require programming the bus controller for the Host RSK.
A[18:1]
5ns
CSn,RDn
Data
Figure 4-5: SRAM read timing
A[18:1]
5ns
CSn,WRn
Data
Figure 4-6: SRAM write timing
20ns
15ns
Valid
20ns
11
5ns
0ns
5ns
8ns 5ns
Valid