Mitsubishi MELSEC-Q Series User Manual page 182

Programmable controller multiple cpu system
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4
COMMUNICATIONS BETWEEN CPU MODULES
(a) Send setting of CPU No.1
(1) Auto refresh setting of CPU No.1
Diagram 4.30 Auto refresh setting related to sending and receiving CPU No.1 data
PLC No.1
Multiple CPU high speed transmission area
PLC No.1
User free area
User free area
1)
Auto refresh area
PLC No.2
User free area
User free area
Auto refresh area
PLC No.3
User free area
User free area
Auto refresh area
Device
Device
B0
B0
to to
CPU No.1 send data
CPU No.1 send data
B1F
B20
B20
to to
CPU No.2 receive area
CPU No.2 receive area
B3F
B40
B40
to to
CPU No.3 receive area
CPU No.3 receive area
B5F
W0
W0
to to
CPU No.1 send data
CPU No.1 send data
W1F
W20
W20
to to
CPU No.2 receive area
CPU No.2 receive area
W3F
W40
W40
to to
CPU No.3 receive area
CPU No.3 receive area
W5F
1) Writing by END processing of CPU No.1
1) Writing by END processing of CPU No.1
2) Sending data from CPU No.1 to CPU No.2 and CPU No.3
2) Sending data from CPU No.1 to CPU No.2 and CPU No.3
3) Reading by END processing of CPU No.2
3) Reading by END processing of CPU No.2
4) Reading by END processing of CPU No.3
4) Reading by END processing of CPU No.3
4
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4.1 Communications between CPU modules using CPU shared memory
4.1.3 Communication by auto refresh using multiple CPU high speed transmission area
(b) Data flow among CPU modules
The following explains the data flow among CPU modules by the auto refresh set
as (a).
1) Flow of sending data from CPU No.1 to other CPUs
<Parameter setting>
Diagram 4.30 shows the settings related to sending and receiving CPU No.1
data ((a) to (c) in Diagram 4.30) in the setting example of auto refresh in
Diagram 4.30.
(b) Receive setting from CPU No.1
(2) Auto refresh setting of CPU No.2
<Flow of sending data from CPU No.1 to other CPUs>
• CPU No.1 writes device data set in Auto refresh (CPU No.1 send data) to
the auto refresh area in CPU No.1 at END processing.
• CPU No.1 sends data in auto refresh area of CPU No.1 to CPU No.2 and
CPU No.3 in multiple CPU high speed transmission cycle.
• CPU No.2 and No.3 read the received data from CPU No.1 to a device set
in Auto refresh (CPU No.1 receive area) at END processing.
Multiple CPU high speed transmission area
PLC No.1
2)
PLC No.2
PLC No.3
PLC No.3
M0
M0
to
CPU No.1 receive area
CPU No.1 receive area
M31
M32
M32
to
CPU No.2 send data
CPU No.2 send data
M63
M64
M64
to
CPU No.3 receive area
CPU No.3 receive area
M95
W0
W0
to
CPU No.1 receive area
CPU No.1 receive area
W1F
W20
W20
to
CPU No.2 send data
CPU No.2 send data
W3F
W40
W40
to
CPU No.3 receive area
CPU No.3 receive area
W5F
Diagram 4.31 Flow of sending data from CPU No.1 to other CPUs
PLC No.2
User free area
User free area
Auto refresh area
User free area
User free area
Auto refresh area
User free area
User free area
Auto refresh area
Device
Device
3)
3)
(b) Receive setting from CPU No.1
(3) Auto refresh setting of CPU No.3
PLC No.3
Multiple CPU high speed transmission area
PLC No.1
User free area
User free area
2)
Auto refresh area
PLC No.2
User free area
User free area
Auto refresh area
PLC No.3
PLC No.3
User free area
User free area
Auto refresh area
Device
Device
B0
B0
to
CPU No.1 receive area
CPU No.1 receive area
B1F
B20
B20
to
CPU No.2 receive area
CPU No.2 receive area
B3F
B40
B40
to
CPU No.3 send data
CPU No.3 send data
B5F
D0
D0
to
CPU No.1 receive area
CPU No.1 receive area
D31
D32
D32
to
CPU No.2 receive area
CPU No.2 receive area
D63
D64
D64
to
CPU No.3 send data
CPU No.3 send data
D95
4)
4)

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