Mitsubishi MELSEC-Q Series User Manual page 155

Programmable controller multiple cpu system
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4
COMMUNICATIONS BETWEEN CPU MODULES
(0
)
G0
H
to
to
( 1FF
)
G511
H
( 200
)
G512
H
to
to
( 7FF
)
G2047
H
( 800
)
G2048
H
to
to
( FFF
)
G4095
H
( 1000
)
G4096
H
to
to
( 270F
)
G9999
H
( 2710
)
G10000
H
to
to
Max.
(5F0F
)
G24335
H
• For Universal model QCPU
CPU shared memory
Host CPU operation
information area
Restricted system area
QCPU
standard
area
Auto refresh area
User setting area
*1
Use-prohibited area
Multiple CPU high speed
*1
transmission area
*1:
The Q02UCPU does not have the use-prohibited area and the multiple CPU
high speed transmission area.
Diagram 4.3 Configuration of CPU shared memory
4.1 Communications between CPU modules using CPU shared memory
Host CPU
Write
Read
: Communication allowed,
: Communication not allowed
4.1.1 CPU shared memory
1
Other CPU
Write
Read
2
3
4
5
6
7
8
4
- 5

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