Change Of The Pll Multiplication Value Under Operation; Table 1.2 Pll Correction (Example); Table 1.3 Pll0Set Setting Value (Example) - Toshiba TXZ+ Series Reference Manual

32-bit risc microcontroller, clock control and operation mode cg-m4g(1)-c
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≤ Maximum Operating Frequency
Note2: There is no Linearity in the frequency by the Fractional part Multiplication setup.
Note3: f
PLL
The main examples of a setting of [CGPLL0SEL] <PLL0SET [23:0]> are shown below.
It multiplies by PLL, and dividing is carried out and the target Clock frequency (f
frequency (fosc).
A dividing value is chosen from 1/2, 1/4, and 1/8.
× Multiplication value) ≤ 400 MHz
Moreover, set up the frequency after multiplication in the following ranges.
200 MHz
(f
OSC
f
(MHz)
osc
8.00
10.00
12.00
16.00
16.00
20.00
24.00

Change of the PLL multiplication value under operation

To change the setting of a PLL multiplication during PLL multiplication clock operation, set
[CGPLL0SEL]<PLL0SEL> to "0" that does not use a PLL multiplication clock. And [CGPLL0SEL] <PLL0ST>
=0 is read to confirm that a multiplication clock setting is not used, then, [CGPLL0SEL] <PLL0ON> is set to "0",
and PLL is stopped.
Then, the multiplication value of [CGPLL0SEL] <PLL0SET[23:0]> is changed, as reset time of PLL, after about
100 μs has elapsed [CGPLL0SEL] <PLL0ON> is set to "1", and operation of PLL is started.
Then, [CGPLL0SEL] <PLL0SEL> is set to "1" after lock-up time (about 400µs) has elapsed.
Finally, [CGPLL0SEL]<PLL0ST> are read and it checks having changed.

Table 1.2 PLL correction (example)

f
(MHz)
<PLL0SET [23:17] >
OSC
(a decimal, an integral value)
8.00
10.00
12.00
16.00
20.00
24.00
The PLL correction value can be calculated below.
f
= 10.0 MHz o'clock, 10.0/0.45 = 22.22  23;
osc

Table 1.3 PLL0SET setting value (example)

Multiplication
Dividing
value
value
50.0000
1/2
40.0000
1/2
33.3150
1/2
25.0000
1/2
12.5000
1/2
20.0000
1/2
16.6575
1/2
17 / 88
Clock Control and Operation Mode
18
23
27
36
45
54
A fractional part is rounded up.
) is generated for input
PLL
f
(MHz)
<PLL0SET[23:0]>
PLL
200
0x245032
200
0x2E9028
199.89
0x36D521
200
0x495019
100
0x49580C
200
0x5B9014
0x6D9A10
199.89
TXZ+ Family
TMPM4G Group(1)
2021-06-30
Rev. 1.1

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