Toshiba TXZ+ Series Reference Manual page 73
32-bit risc microcontroller, clock control and operation mode cg-m4g(1)-c
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- Reference manual (64 pages) ,
- Reference manual (52 pages) ,
- Reference manual (72 pages)
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[FCRACCR] (RAM Access Control Register)
Bit
Bit Symbol
31:14
-
13:12
-
11:10
-
9:8
-
7:6
-
5:4
RAMLC1[1:0]
3:2
-
1:0
-
Note1: Rewrite the contents of this register on the program code in the Flash memory.
Note2: To rewrite this register, follow the procedure below:
1.
Write the specific code (0xA74A9D23) to [FCKCR].
2.
Rewrite data of [FCRACCR]<RAMLC1[1:0]> within 16 clocks after Procedure 1.
3.
After wrote, check read data is same as wrote data.
Note3: When using clock gear, set this register according to the maximum frequency in the application. Do not
change the setting even if the frequency is lowered with the clock gear.
After reset
Type
0
R
Read as "0"
00
R/W
Write as "00"
0
R
Read as "0"
00
R/W
Write as "00"
0
R
Read as "0"
Access control to RAM1, RAM2
00: 1clock (fsysh ≤ 160MHz)
00
R/W
01: 2clocks (fsysh > 160MHz)
Others: Reserved
0
R
Read as "0"
00
R/W
Write as "00"
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TMPM4G Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2021-06-30
Rev. 1.1
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