[Cgfsysmena] (Middle Speed Clock Supply And Stop Register A For Fsysm) - Toshiba TXZ+ Series Reference Manual

[CGFSYSMENA] (Middle speed clock supply and stop register A for fsysm)

Bit Bit Symbol
31 IPMENA31
30 IPMENA30
29 IPMENA29
28 IPMENA28
27 IPMENA27
26 IPMENA26
25 IPMENA25
24 IPMENA24
23 IPMENA23
22 IPMENA22
21 IPMENA21
20 IPMENA20
19 IPMENA19
18 IPMENA18
17 IPMENA17
16 IPMENA16
15 IPMENA15
14 IPMENA14
13 IPMENA13
12 IPMENA12
11 IPMENA11
After
Type
reset
Clock enable of I2C ch2
0 R/W 0: Clock stop
1: Clock supply
Clock enable of I2C ch1
0 R/W 0: Clock stop
1: Clock supply
Clock enable of I2C ch0
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch5
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch4
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch3
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch2
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch1
0 R/W 0: Clock stop
1: Clock supply
Clock enable of UART ch0
1 R/W 0: Clock stop
1: Clock supply
Clock enable of TSPI ch8
0 R/W 0: Clock stop
1: Clock supply
Clock enable of TSPI ch7
0 R/W 0: Clock stop
1: Clock supply
Clock enable of TSPI ch6
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch13
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch12
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch11
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch10
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch09
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch08
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch07
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch06
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch05
0 R/W 0: Clock stop
1: Clock supply
42 / 88
TMPM4G Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2021-06-30
Rev. 1.1