Change Of The Pll Multiplication Value Under Operation; Table 1.3 Pll0Set Setting Value (Example) - Toshiba TXZ+ TMPM4KLFYAUG Reference Manual

The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below.
It multiplies by PLL, and dividing is carried out and the target Clock frequency (f
frequency (fosc).
A dividing value is chosen from 1/2, 1/4, and 1/8.
Moreover, set up the frequency after multiplication in the following ranges.
200 MHz ≤ (fosc × Multiplication value) ≤ 400 MHz
fosc (MHz)
6.00
8.00
10.00
12.00

1.2.5.3. Change of the PLL multiplication value under operation

To change the setting of a PLL multiplication during PLL multiplication clock operation, set [CGPLL0SEL]
<PLL0SEL> to "0" that does not use a PLL multiplication clock. And [CGPLL0SEL]<PLL0ST> =0 is read to
confirm that a multiplication clock setting is not used, then, [CGPLL0SEL]<PLL0ON> is set to "0", and PLL is
stopped.
Then, the multiplication value of [CGPLL0SEL]<PLL0SET[23:0]> is changed, as reset time of PLL, after about
100 µs has elapsed, [CGPLL0SEL]<PLL0ON> is set to "1", and operation of PLL is started.
Then, [CGPLL0SEL]<PLL0SEL> is set to "1" after lock-up time (about 400µs) has elapsed.
Finally, [CGPLL0SEL]<PLL0ST> is read and it checks having changed.

Table 1.3 PLL0SET setting value (example)

Multiplication Dividing
value value
53.3125 1/2
40.0000 1/2
32.0000 1/2
26.6250 1/2
16 / 68
Clock Control and Operation Mode
) is generated for input
PLL
f (MHz) <PLL0SET[23:0]>
PLL
159.94 0x1C1535
160 0x245028
160 0x2E9020
159.75 0x36DA1A
TXZ+ Family
TMPM4K Group(2)
2023-12-25
Rev. 3.0