Toshiba TXZ+ Series Reference Manual page 6

TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
List of Tables
Table 1.1 Details of a [CGPLL0SEL] <PLL0SET [23:0]>setup................................................................ 16
Table 1.2 PLL correction (example) ......................................................................................................... 17
Table 1.3 PLL0SET setting value (example) ........................................................................................... 17
Table 1.4 Clock domains of CPU and peripherals ................................................................................... 19
Table 1.5 Time interval for changing System clock ................................................................................. 19
Table 1.6 Example of operating frequency .............................................................................................. 20
Table 1.7 Operating frequency examples of High speed and Middle speed system clocks ................... 20
Table 1.8 Time interval for changing prescaler clocks ............................................................................ 23
Table 1.9 Low Power Consumption mode selection................................................................................ 25
Table 1.10 Block operation status in each Low Power Consumption mode ........................................... 26
Table 1.11 Release source list ................................................................................................................. 31
Table 1.12 Warming up ............................................................................................................................ 32
Table 1.13 [CGFSYSENA] register corresponding to each product ........................................................ 50
Table 1.14 [CGFSYSMENA] register corresponding to each product ..................................................... 51
Table 1.15 [CGFSYSMENB] register corresponding to each product ..................................................... 52
Table 1.16 [CGFSYSMENC] register corresponding to each product .................................................... 53
Table 1.17 [CGFCEN] register corresponding to each product ............................................................... 54
Table 2.1 TMPM4GxF20 Single chip mode ............................................................................................. 63
Table 2.2 TMPM4GxF20 Single boot mode............................................................................................. 64
Table 2.3 TMPM4GxF15 Single chip mode ............................................................................................. 65
Table 2.4 TMPM4GxF15 Single boot mode............................................................................................. 66
Table 2.5 TMPM4GxF10 Single chip mode ............................................................................................. 67
Table 2.6 TMPM4GxF10 Single boot mode............................................................................................. 68
Table 2.7 TMPM4GxFD Single chip mode .............................................................................................. 69
Table 2.8 TMPM4GxFD Single boot mode .............................................................................................. 70
Table 2.9 Peripheral Area ........................................................................................................................ 71
Table 2.10 The number of clocks to access each RAM .......................................................................... 72
Table 3.1 A reset factor and the range initialized .................................................................................... 86
Table 4.1 Revision history ........................................................................................................................ 87
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