Toshiba TXZ+ Series Reference Manual page 27

32-bit risc microcontroller, clock control and operation mode cg-m4g(1)-c

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Note3: A port state when the [RLMSHTDNOP] <PTKEEP> is set to "1" is held.

Note4: This operation is enabled by setting LTTMR as a sampling clock.

Note5:

This function is enabled when [RLMLOSCCR]<POSCEN> is set to "1".

Note6: It becomes a data hold when peripheral functions (DMA etc.) which carry out data access (R/W), except CPU,

are not connected on the bus matrix.

Note7:

RLM means the registers to control the power, the low speed oscillator, and others in the region where the power is not cut

off.

Clock Control and Operation Mode

27 / 88

TXZ+ Family

TMPM4G Group(1)

2021-06-30

Rev. 1.1

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