[Cgfsysmenc] (Middle Speed Clock Supply And Stop Register C For Fsysm) - Toshiba TXZ+ Series Reference Manual

[CGFSYSMENC] (Middle speed clock supply and stop register C for fsysm)

Bit Bit Symbol
31:17 -
16 IPMENC16
15 IPMENC15
14:10 -
9 IPMENC09
8 IPMENC08
7 IPMENC07
6 IPMENC06
5 IPMENC05
4 IPMENC04
3 IPMENC03
2 IPMENC02
1 IPMENC01
0 IPMENC00
Note1: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.
Note2: Write "0" for bit of function that does not exist in TMPM4GQ and TMPM4GN. Refer to "1.5. Information
according to product" for detail.
After
Type
reset
0 R Read as "0"
Clock enable of T32A ch15
0 R/W 0: Clock stop
1: Clock supply
Clock enable of T32A ch14
0 R/W 0: Clock stop
1: Clock supply
00000 R/W Write as "00000"
Clock enable of EI2C ch4
0 R/W 0: Clock stop
1: Clock supply
Clock enable of EI2C ch3
0 R/W 0: Clock stop
1: Clock supply
Clock enable of EI2C ch2
0 R/W 0: Clock stop
1: Clock supply
Clock enable of EI2C ch1
0 R/W 0: Clock stop
1: Clock supply
Clock enable of EI2C ch0
0 R/W 0: Clock stop
1: Clock supply
Clock enable of TSSI ch1
0 R/W 0: Clock stop
1: Clock supply
Clock enable of TSSI ch0
0 R/W 0: Clock stop
1: Clock supply
Clock enable of FIR
0 R/W 0: Clock stop
1: Clock supply
Clock enable of I2S ch1
0 R/W 0: Clock stop
1: Clock supply
Clock enable of I2S ch0
0 R/W 0: Clock stop
1: Clock supply
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TMPM4G Group(1)
Clock Control and Operation Mode
Function
TXZ+ Family
2021-06-30
Rev. 1.1