Toshiba TXZ+ Series Reference Manual page 3

NORMAL → STOP2 → RESET → NORMAL Operation mode transition ...................................................................... 35
Explanation of a register .................................................................................................................................. 36
Register list ................................................................................................................................................................. 36
Detail of Register ........................................................................................................................................................ 37
[CGPROTECT] (CG write protection register) ............................................................................................................... 37
[CGOSCCR] (Oscillation control register) ...................................................................................................................... 37
[CGSYSCR] (System clock control register) .................................................................................................................. 38
[CGSTBYCR] (Standby control register) ....................................................................................................................... 39
[CGPLL0SEL] (PLL selection register for fsys) .............................................................................................................. 39
[CGWUPHCR] (High speed oscillation warming up register) ......................................................................................... 40
[CGWUPLCR] (Low speed oscillation warming up register) .......................................................................................... 40
[CGFSYSMENC] (Middle speed clock supply and stop register C for fsysm) ................................................................ 41
[CGFSYSMENA] (Middle speed clock supply and stop register A for fsysm) ................................................................ 42
[CGFSYSMENB] (Middle speed clock supply and stop register B for fsysm) .............................................................. 44
[CGFSYSENA] (High speed clock supply and stop register A for fsysh) ..................................................................... 46
[CGFCEN] (Clock supply and stop register for fc) ....................................................................................................... 47
[CGSPCLKEN] (Clock supply for ADC and Debug circuit Register) ............................................................................ 47
[CGEXTEND2] (Function extension register 2) ........................................................................................................... 48
[RLMLOSCCR] (Low speed oscillation and Internal High speed oscillation 2 clock control register) ........................... 48
[RLMSHTDNOP](Power supply cut off control register) .............................................................................................. 49
[RLMPROTECT](RLM write protection register) .......................................................................................................... 49
Information according to product ..................................................................................................................... 50
[CGFSYSENA] ........................................................................................................................................................... 50
[CGFSYSMENA] ........................................................................................................................................................ 51
[CGFSYSENB] ........................................................................................................................................................... 52
[CGFSYSENC] ........................................................................................................................................................... 53
[CGFCEN] .................................................................................................................................................................. 54
2. Memory Map ............................................................................................................................................... 55
Outline .............................................................................................................................................................. 55
TMPM4GxF20 ............................................................................................................................................................ 56
TMPM4GxF15 ............................................................................................................................................................ 57
TMPM4GxF10 ............................................................................................................................................................ 58
TMPM4GxFD.............................................................................................................................................................. 59
Bus Matrix ........................................................................................................................................................ 60
Structure ..................................................................................................................................................................... 61
Single chip mode ........................................................................................................................................................... 61
Single boot mode .......................................................................................................................................................... 62
Connection table ......................................................................................................................................................... 63
Code area / SRAM area / SMIF area / External bus area .............................................................................................. 63
Peripheral Area ............................................................................................................................................................. 71
RAM Access ............................................................................................................................................................... 72
Control Registers .......................................................................................................................................................... 72
3. Reset and Power Control ............................................................................................................................ 74
Outline .............................................................................................................................................................. 74
Function and Operation ................................................................................................................................... 74
Clock Control and Operation Mode
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TXZ+ Family
TMPM4G Group(1)
2021-06-30
Rev. 1.1