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TP/SW/LED/FUSE
4.6 TP/SW/LED/FUSE
4.6.1 MAIN CONTROL BOARD TEST POINTS
TP No.
Signal
TP101
GND
Ground
TP102
GND
Ground
X-
TP103
TP X-axis ground terminal
X+
TP X-axis power terminal
TP104
TP105
Y-
TP Y-axis ground terminal
Y+
TP106
TP Y-axis power terminal
XCK
LCD data shift lock
TP109
LP
LCD latch pulse output
terminal
TP110
YD
LCD Y driver frame start
TP111
signal
/DME
Identifies the end of IPU
image transfer during area
processing.
TP124
TP130
GND
Ground
/RESET
Open-drain bi-directional
signal that serves as the
external device reset output
TP131
from the CPU and as the
hardware reset input from
the reset IC.
/FGATE
Input terminal for /BFGATE
TP134
interrupts from the write
control board
BLTPTN Transfer belt mark input
TP137
signal
/DSACK1 Hand-shake signal for 16-bit
devices
TP138
/DSACK0 Hand-shake signal for 8-bit
devices
TP141
TP143
GND
Ground
CLK
System clock output to
TP148
external devices
/AS
Asserted while a valid
TP153
address is present on the
address bus.
Stand-by
Description
4-22
Remarks
(V)
0 to 5.0
0 to 5.0
0 to 5.0
0 to 5.0
In the press sense
mode, held at the
VCC level when
released and lowered
to 3V or lower when
pressed.
0 to 5.0
0 to 5.0
0 to 5.0
Data is shifted into the
X driver on the falling
edge of this clock.
0 to 5.0
Data is latched into
the driver's shift
register to turn on the
Y driver for that line
on the falling edge of
this signal.
0 to 5.0
0 to 5.0
Hardware-asserted at
the end of transfer
and disasserted when
the register is written
under software
control. Active L
0
0 to 5.0
Active L
0 to 5.0
Active L
0 to 5.0
Active H
0 to 5.0
Indicates that the
CPU is ready for
completing the bus
cycle. Active L
0 to 5.0
Indicates that the
CPU is ready for
completing the bus
cycle. Active L
0
0 to 5.0
Set to 19.6608 MHz
when the CPU is
started.
0 to 5.0
Active L
24 February, 1999
TP
Implementation
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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