Avnet SMARC MSC SM2S-IMX8MINI User Manual page 42

The I²C bus driven by CPU core function has the following key features:
• Compatible with I2C bus standard
• Multimaster operation
• Software programmability for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
•
Calling address identification interrupt
• Start and stop signal generation/detection
•
Repeated Start signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
• Data rates up to 100kbits/s in Standard mode and 400kbits/s in Fast mode
Pin
Signal Signal Level
Type
I2C_GP_CK O OD 1.8V CMOS
I2C_GP_DAT I/O OD 1.8V CMOS
SMB_ALERT_1V8# I OD 1.8V CMOS
MSC SM2S-IMX8MINI
User Manual
Table 17: I²C Signal Description
Pin on Pin name on Power
i.MX8M Mini i.MX8M Mini Tolerance
E10 I2C2_SCL 1.8V
F10 I2C2_SDA 1.8V
AF9 SPDIF_TX 1.8V
PU/PD Description
PU 2.2k 1.8V General Purpose SMB clock output
PU 2.2k 1.8V General Purpose SMB data I/O line
PU 2.2k 1.8V Interrupt Signal (GPIO5_IO03)
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