Pci Express; Usb - Avnet SMARC MSC SM2S-IMX8MINI User Manual

4.3 PCI Express

The i.MX8M Mini SoC supports PCIe x1 Gen2 lane.*
Signal Pin Type Signal Level
PCIE_A_TX+ O LVDS PCIe
PCIE_A_TX-
PCIE_A_RX+ I LVDS PCIe
PCIE_A_RX-
PCIE_A_REFCK+ O LVDS PCIe
PCIE_A_REFCK-
PCIE_WAKE# I 3.3V CMOS
PCIE_A_RST# O PP 3.3V CMOS
*
NOTE: In case GBE1 Interface is implemented on the module the PCIe Interface will no longer be available. Pins can be left unconnected

4.4 USB

The USB controller supports USB 2.0.
Depending on the module variant the following USB lane options are available:
•
Option 1 with USB 2.0 Hub:
•
Option 2 without USB 2.0 Hub: USB[0] = USB 2.0 host/device OTG compliant
MSC SM2S-IMX8MINI
User Manual
Table 8: PCIe Signal Description
Pin on Pin name on
i.MX8M Mini i.MX8M Mini
B20 PCIE_TXN_P
A20
PCIE_TXN_N
B19 PCIE_RXN_P
A19
PCIE_RXN_N
B21 PCIE_CLK_N
A21
PCIE_CLK_P
N27 NAND_RE_B
K27 NAND_CLE
USB[0] = USB 2.0 host/device OTG compliant
USB[1:4] = USB 2.0 host
USB[1] = USB 2.0 host.
Power
PU/PD Description
Tolerance
According to PCI Express Differential Transmit Pairs. AC
PCIe spec coupled on module
According to PCI Express Differential Receive Pairs
PCIe spec
According to PCI Express Reference Clock. AC coupled
PCIe spec on module. Clock enabled by default.
3.3V PU 10k PCI Express Wake signal. Asserted by
device when requesting wake up.
(CPU GPIO3_IO15)
3.3V PCI Express Reset output signal.
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