Reference Design; Description; Clock; Reset - ST STM32F20 Series Application Note

AN3320
6

Reference design

6.1

Description

The reference design shown in
integrated microcontroller running at 120 MHz, that combines the Cortex
CPU core with 1 Mbyte of embedded Flash memory and up to 128 + 4 Kbytes of high-speed
.
SRAM
This reference design can be tailored to any other STM32F20xxx/21xxx device with different
package, using the pins correspondence given in
packages.
6.1.1

Clock

Two clock sources are used for the microcontroller:
●
LSE: X1– 32.768 kHz crystal for the embedded RTC
●
HSE: X2– 25 MHz crystal for the STM32F20xxx/21xxx microcontroller
Refer to
6.1.2

Reset

The reset signal in
●
Reset button (B1)
●
Debugging tools via the connector CN1
Refer to
6.1.3

Boot mode

The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page
Note: In low-power mode (more specially in Standby mode) the boot mode is mandatory to be
able to connect to tools (the device should boot from the SRAM).
6.1.4

SWJ interface

The reference design shows the connection between the STM32F20xxx/21xxx and a
standard JTAG connector. Refer to
Note: It is recommended to connect the reset pins so as to be able to reset the application from
the tools.
6.1.5

Power supply

Refer to
Section 2: Clocks on page
Figure 14 is active low. The reset sources include:
Section 1.3: Reset & power supply supervisor on page
Section 1: Power supplies on page
Figure 14, is based on the STM32F207IF(H6), a highly
Table 6: Reference connection for all
12.
16.
Section 4: Debug management on page
6.
Doc ID 18267 Rev 2
Reference design
™
-M3 32-bit RISC
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