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P
S
OWER
TATES
CPU power states will affect voltage rails driving DIO circuits as described below:
DIOs and their pull-up resistors will remain powered in all CPU power states (except
when power is turned off). The DIO power (which includes the pullup voltage) can be
controlled (the same power used for the 8x GPIOs on the CBR-4005 paddleboard) using
an FPGA register setting. By default, they power-down in sleep modes but can be
configured to always stay on.
Power control during CPU power states on user devices connected to DIO lines is
dependent on the application design. These external devices would likely remain
powered unless a power-down mechanism is designed into the system.
Care must be taken when powered DIO signals are connected to un-powered DIO
signals. Significant voltage and current can be leaked from a powered system to an un-
powered system causing unpredictable results. Current limiting and/or diode isolation
can help.
C
ABLES
Cabling issues will affect the usable speed of DIO signals.
These are single-ended drivers/receivers.
Cabling crosstalk can be a problem with fast edge rates. The DIOs are slew-rate limited
and have 50 Ω source terminators to minimize crosstalk and reflections.
EPM-31 Hardware Reference Manual
Multi-purpose I/O
42
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