Cabling; Table 8: J4 I/O Connector Pinout And Pin Orientation - VersaLogic BayCat VL-EPM-31ECP Hardware Reference Manual

Table 8 provides the pinout of the user I/O connector.
Notes:
1. This 3.3 V power goes off in sleep modes. The SPKR# uses this power as should the
PLED# (there is no requirement for PLED# to use this power, but the CBR-4005
paddleboard does).
2. This 3.3 V power can be turned on our off similar to the 3.3V power to the Mini Card via
the FPGA (can go off in sleep modes or always stay on; by default it goes off in sleep
modes). It is used for the 10 kΩ pullup resistor power on the 8x GPIOs and usually for the
2x Ethernet LEDs, however, the Ethernet LEDs can be powered by a 3.3 V power source.
C
ABLING
An adapter cable, part number CBR-4005A, is available for connecting the CBR-4005B
paddleboard to the EPM-31. This is a 12-inch, Pico-Clasp 40-pin to 40-pin cable
If your application requires a custom cable, the following information will be useful:
2
I C
Pins 21 and 23 of the J4 User I/O connector connect to the first of the seven I
Atom "Bay Trail" processor. The EPM-31 has a 3.3 V I
interface are included in the EPM-31 design. The 3.3 V power for this interface is the same as
that used for the digital I/O interface. By default, this power is turned off when the processor is
in a sleep state.
EPM-31 Hardware Reference Manual

Table 8: J4 I/O Connector Pinout and Pin Orientation

Pin Signal
1 +5 V
3 USB0_P
5 USB0_N
7 +5V
9 USB2_P
11 USB2_N
13 +3.3 V (Note 1)
15 SPKR#
17 PWR_BTN#
19 GND
21 I2C Clock
23 I2C Data
25 GND
27 FPGA GPIO1
29 FPGA GPIO3
31 GND
33 FPGA GPIO5
35 FPGA GPIO7
37 +3.3 V (Note 2)
39 ETH0 LED
EPM-31 Board Connector
Molex 501571-4007
Pin Signal
2 GND
4 USB1_P
6 USB1_N
8 GND
10 USB3_P
12 USB3_N
14 GND
16 PLED#
18 RST_BTN#
20 GND
22 V_BATT
24 RETURN_BATT
26 GND
28 FPGA GPIO2
30 FPGA GPIO4
32 GND
34 FPGA GPIO6
36 FPGA GPIO8
38 GND
40 ETH1 LED
Mating Connector
Molex 501189-4010
2
C ports on the Intel
2
C interface. The required pullups for this
Multi-purpose I/O
39