Key Features - Altera DE5-NET User Manual

1 . 2 K e y F e
1 . 2 K e y F e
The following hardware is implemented on the DE5-Net board:
 FPGA

Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)
 FPGA Configuration

On-Board USB Blaster II or JTAG header for FPGA programming

Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
 General user input/output:

10 LEDs

4 push-buttons

4 slide switches

2 seven-segment displays
 Clock System

50MHz Oscillator

Programmable oscillators Si570, CDCM61001 and CDCM61004

One SMA connector for external clock input

One SMA connector for clock output
 Memory

DDR3 SO-DIMM SDRAM

QDRII+ SRAM

FLASH
 Communication Ports

Four SFP+ connectors

Two Serial ATA host ports

Two Serial ATA device ports

PCI Express (PCIe) x8 edge connector

One RS422 transceiver with RJ45 connector
DE5-Net User Manual
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a t u r e s
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www.terasic.com
June 20, 2018